DS643 Datasheet, PDF (174/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
2. Assume the NPI width is 64 and the memory is a 64-bit DDR device. In this case, the memory datapath can
drain the Write Data FIFO at twice the maximum rate at which it can be filled. If the user design pushes in the
Write data on every NPI clock cycle, the address request can be generated after half of the write data is pushed
in. This ensures the Write Data FIFO does not underrun.
NPI Clock Requirements
The NPI PIM must run at the same frequency as the MPMC. Support for any other frequency must be implemented
in the custom PIM.
Configuring the NPI PIM
The NPI PIM is configured through the MPMC interface. Review the IP Configuration Graphical User Interface,
page 209 for details on how to configure a PIM.
NPI Timing Diagrams
The following timing diagrams illustrate the functionality of the port interfaces. In the actual design signal names
are prefixed with PIM<Port_Num>_, but in this section this prefix has been omitted for readability. Only a small
sampling of possible timing diagrams are shown here. For example:
• 64-word burst transfers are not shown. These are very similar to the 32-word burst transfers, with the
exception that there are more data beats.
• 32-bit NPI and 64-bit NPI are very similar. Differences are in the permitted address alignment and the number
of data beats required to complete a particular transfer.
• Because Spartan-6 FPGAs utilize an NPI-to-MCB interface converter, the timing portrayed in these diagrams
might be slightly different.
64-bit NPI Timing Diagrams
The following 64-bit NPI timing diagrams are described and illustrated:
• Doubleword Write
• Doubleword Read
• 8-Word, Cacheline Write
• 8-Word, Cacheline Read
• 32-Word, Burst Write
• 32-Word, Burst Read
• 8-Word, Cacheline Write with Almost Full Flag Asserted
• 8-Word, Cacheline Read with Back-to-Back Transfers
• 32-Word, Burst Read with Read FIFO Flush Asserted
DS643 February 22, 2013
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