DS643 Datasheet, PDF (163/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Data transfers to and from the VFBC data FIFOs are controlled by the command interface. Commands are written
into the command interface FIFO in 4-word packets. This four word packet controls the direction (Read or Write)
and the 2D size of the transfer, and also includes the following information: start address of the 2D transfer, X-size
in bytes, Y-size in lines, and the width (Stride) of the video frame.
The VFBC data and address signals are labeled with little-endian bit/byte ordering as illustrated in Figure 7,
page 84. The Least Significant Bit (LSB) of a 32-bit word is bit zero.
VFBC Command Interface
The command interface is implemented as an asynchronous FIFO. Commands are written into the command
interface FIFO in 4-word packets. Each command packet word is pushed onto the command FIFO during the clock
cycle the VFBC<Port_Num>_Cmd_Write signal is active. It is not necessary to Write the command words during
consecutive clock cycles; VFBC acts on the commands after the last command word is written. The command
packets can be written at the same time as data transfers to the data interface FIFOs. Table 85 shows the command
packet data structure.
Table 85: Command Packet Data Structure
Command Packet
Command Word 0
Command Word 1
Command Word 2
31:15
Reserved
14:0
X Size⁽¹⁾
31
30:0
31:24
Write_NotRead Start Address⁽¹⁾ Reserved
23:0
Y Size
Command Word 3
31:24
Reserved
23:0
Stride⁽¹⁾
Notes:
1. The X Size, Start Address and Stride must be aligned to a 32-word boundary. These values must be a multiple of 128 bytes and
require that bits [6:0] be '0'.
The VFBC divides each 2D transfer into 32-word transfers for the MPMC. Figure 39 shows a video frame stored
linearly in external memory. The frame contains a rectangular region of interest to be transferred by the VFBC.
DS643 February 22, 2013
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