DS643 Datasheet, PDF (6/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 2: System Parameters (Cont’d)
Parameter Name
C_SPECIAL_BOARD
C_SKIP_SIM_INIT_DELAY^(5),(7)
C_STATIC_PHY_RDEN_DELAY⁽³⁾
C_STATIC_PHY_RDDATA_CLK_SEL⁽³⁾
C_STATIC_PHY_RDDATA_SWAP_RISE⁽³⁾
C_USE_MIG_FLOW
C_USE_STATIC_PHY⁽¹⁰⁾
C_WR_DATAPATH_TML_PIPELINE ^(7),(10)
C_WR_TRAINING_PORT⁽⁴⁾
Default
Value
NONE
0
5
0
0
0
0
1
0
Allowable
Values
S3E_STKIT,
S3E_1600E,
S3A_STKIT,
NONE
0,1
0-15
0,1
0,1
0,1
0,1
0,1
0-7
Description
Xilinx special physical layer for Spartan-3E and
Spartan-3A FPGA boards.
For simulation only, allows a shorter initialization
sequence. On Virtex-6 FPGAs, when this
parameter is enabled, MIG PHY parameters are set
as follows:
• MEM_CAL_WIDTH = HALF
• OCB_MONITOR = OFF
• SIM_INIT_OPTION = SKIP_PU_DLY
• SIM_CAL_OPTION = FAST_CAL
Sets power-on or reset value of RDENDELAY
register.
Sets power-on or reset value of RDDATA_CLK_SEL
register.
Sets power-on or reset value of
RDDATA_SWAP_RISE register.
Enables and disables the use of the integrated MIG
GUI flow from the MPMC IP Configuration GUI.
0 = Normal MPMC flow without integrated MIG GUI
flow.
1 = Enables the use of the integrated MIG GUI Flow
for running the MIG GUI from the MPMC IP
Configuration GUI.
This setting also links the area, timing, and I/O
placement constraints automatically from the MIG
GUI with the MPMC EDK project. See Integrated
MIG GUI Flow, page 91 for more information.
Enables or disables a software controlled interface
for the physical layer calibration (Static PHY):
0 = Static PHY Disabled.
1 = Static PHY Enabled.
Static PHY is automatically enabled when
C_MEM_TYPE = SDRAM.
Enables or disables the Write Data Path Timing
Management:
0 = Write Data Path Timing Management Logic
Pipeline Disabled.
1 = Write Data Path Timing Management Logic
Pipeline Enabled.
Specifies the port where the Write FIFO is used for
memory initialization. This value is an automatically
calculated parameter that can be overwritten. If the
parameter is set by the user, it is not calculated.
Notes:
1. When C_ALL_PIMS_SHARE_ADDRESSES is set to 1, C_MPMC_BASEADDR is used for all ports for memory access addressing and
C_SDMA_CTRL_BASEADDR is used for all SDMA PIMs (if applicable).
If set to 0, the C_PIMx_BASEADDR, and C_SDMA_CTRLx_BASEADDR parameters are used.
2. Valid if C_PM_ENABLE is set to 1.
3. Valid when using Static PHY (C_USE_STATIC_PHY = 1).
4. Valid when using MIG-based Virtex-4/Virtex-5 FPGA DDR/DDR2 PHY.
5. Memory calibration simulation times vary based on C_MEM_WIDTH and C_FAMILY and assume C_SKIP_SIM_INIT_DELAY = 1:
Virtex-4 FPGA DDR = 90 us
Virtex-4 FPGA DDR2 = 50 us
Virtex-5 FPGA DDR = 1400 us
Virtex-5 FPGA DDR2 =100 us
6. Valid only if the Performance Monitors (PM), Error Correction Code (ECC), Debug registers, or Static PHY feature is enabled.
7. Not supported on Spartan-6 FPGAs.
8. Spartan-6 FPGAs only.
9. Virtex-6 FPGAs only.
10. Spartan-3, Virtex-4, and Virtex-5 FPGAs only.
DS643 February 22, 2013
www.xilinx.com
6
Product Specification