DS643 Datasheet, PDF (160/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
X-Ref Target - Figure 37
PPC440MC<Port_Num>_MIMCAddress[0:35] (1)
PPC440MC<Port_Num>_MIMCAddressValid
PPC440MC<Port_Num>_MIMCByteEnable[0:15]
PPC440MC<Port_Num>_MIMCWriteData[0:127]
PPC440MC<Port_Num>_MIMCWriteDataValid
PPC440MC<Port_Num>_MIMCReadNotWrite
M
N
I ^{PPC440MC<Port_Num>_MCMIAddrReadytoAccept}
PPC440MC PIM
P
B
I
PPC440MC<Port_Num>_MCMIReadData[0:127]
PPC440MC<Port_Num>_MCMIReadDataValid
X10929
Figure 37: PPC440MC Block Diagram
The functional units within the PPC440MC PIM are:
• Addr Path - generates address, address request (MPMC_PIM_AddrReq), readnotwrite, and size
(MPMC_PIM_Size) signals. The Addr Path also generates addressreadytoaccept information for
PPC440MC.
• Write Data Path - generates writedata, writedatvalid (push) and byteenable.
• Read Data Path - generates readdata and readdatavalid for PPC440MC. The Read Data Path also generates
the RdFIFO_POP and RdModWr.
PPC440MC Design Implementation
The PPC440MC PIM is available in the Virtex-5 FXT FPGAs only.
PPC440MC Parameter and Port Dependencies
Dependencies exist between the PPC440MC PIM core design parameters and the I/O signals. In addition, when
certain features are parameterized out of the design, the related logic is no longer a part of the design. The unused
input signals and related output signals are set to a specified value.
DS643 February 22, 2013
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Product Specification