DS643 Datasheet, PDF (85/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Little-Endian Label Settings
Table 60: Little-Endian Bit and Byte Label Settings
Description
Memory
Type
MPMC Signal [MSB:LSB]
Memory Signal [MSB:LSB]
Data Bus
All
Bank Address All
<memory_type>_DQ
[C_MEM_DATA_WIDTH-1:0]
<memory_type>_BankAddr
[C_MEM_BANKADDR_WIDTH-1:0]
DQ[C_MEM_DATA_WIDTH-1:0]
BA[C_MEM_BANKADDR_WIDTH-1:0]
Address
All
<memory_type>_Addr
[C_MEM_ADDR_WIDTH-1:0]
A[C_MEM_ADDR_WIDTH-1:0]
Data
Data Strobe
All
<memory_type>_DQ
[C_MEM_DATA_WIDTH-1:0]
DDR / DDR2
<memory_type>_DQS
[C_MEM_DQS_WIDTH-1:0]
DQ[C_MEM_DATA_WIDTH-1:0]
UDQS,LDQS (Replicate for number of memory
parts)
Differential Data
Strobe
DDR2
Data Mask
All
<memory_type>_DQS_n
[C_MEM_DQS_WIDTH-1:0]
<memory_type>_DM
[C_MEM_DM_WIDTH-1:0]
UDQS#,LDQS# (Replicate for number of
memory parts)
UDM,LDM (Replicate for number of memory
parts)
ECC Check Bits All
<memory_type>_DQ
[C_MEM_DATA_WIDTH
+C_MPMC_CTRL_DATA_WIDTH
-1:C_MEM_DATA_WIDTH]
DQ_ECC[C_MPMC_CTRL_DATA_WIDTH-1:0]
ECC Data
Strobe
<memory_type>_DQS[C_MEM_DQS_WIDTH+C_M
DDR / DDR2 PMC_CTRL_DQS_WIDTH-1:C_MEM_DQS_WIDTH DQS_ECC[C_MPMC_CTRL_DQS_WIDTH-1:0]
]
Differential ECC
Data Strobe
DDR2
ECC Data Mask All
<memory_type>_DQS_n
[C_MEM_DQS_WIDTH
+C_MPMC_CTRL_DQS_WIDTH
-1:C_MEM_DQS_WIDTH]
<memory_type>_DM
[C_MEM_DM_WIDTH
+C_MPMC_CTRL_DM_WIDTH
-1:C_MEM_DM_WIDTH]
DQSn_ECC
[C_MPMC_CTRL_DQS_WIDTH-1:0]
DM_ECC[C_MPMC_CTRL_DM_WIDTH-1:0]
DS643 February 22, 2013
www.xilinx.com
85
Product Specification