DS643 Datasheet, PDF (119/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
MCB Performance Mode
For DDR2 memory, depending on the voltage regulation on the board, the MCB operates in one of two performance
modes.
• By default, the MCB operates in DDR2 memory STANDARD performance mode which limits the maximum
frequency of MPMC_Clk_Mem_2x (these limits are specified in the Spartan-6 FPGA data sheet). The setting is
inferred by the ISE tools to be CONFIG MCB_PERFORMANCE = STANDARD.
• Alternatively, with better voltage regulation on the board, the MCB DDR2 interface can be operated in
EXTENDED performance mode which supports higher maximum frequencies for MPMC_Clk_Mem_2x. When
using EXTENDED mode, you must manually set “CONFIG MCB_PERFORMANCE = EXTENDED” in the
system.ucf as described in the “MCB Performance” section in UG625, Constraints Guide.
Note:
• For DDR3 memory, add CONFIG MCB_PERFORMANCE = EXTENDED to the UCF because the
CONFIG MCB_PERFORMANCE = STANDARD setting for DDR3 is generally used for “ES” grade silicon.
• The MPMC does not implement a DRC to check the frequency of MPMC_Clk_Mem_2x against the CONFIG
MCB_PERFORMANCE setting in the system.ucf.
Spartan-6 FPGA C_MCB_LOC Parameter
The C_MCB_LOC parameter has possible values of MEMC1, MEMC2, MEMC3, and MEMC4.It is used to specify which MCB
bank to which to locate the MPMC. Table 64 and Table 65 list the mapping from FPGA bank number to C_MCB_LOC
parameter value for two MCB devices and four MCB devices.
Table 64: Two MCB Devices
FPGA Bank Number where MCB is located
Bank 1
Bank 3
C_MCB_LOC Parameter Value
MEMC1
MEMC3
Table 65: Four MCB Devices
FPGA Bank Number where MCB is located
Bank 1
Bank 3
Bank 4
Bank 5
C_MCB_LOC Parameter Value
MEMC2
MEMC3
MEMC4
MEMC1
Spartan-6 FPGA Reset Logic
The basic MPMC core and each of the MPMC PIMs have a reset input. Internally, these resets are ORed together to
create the master reset for the entire MPMC (including PIMs).
Note: It is not possible to reset an individual PIM or PORT of the MPMC without resetting everything.
The master reset, MPMC_Rst, is internally registered and synchronized before being distributed throughout the
MPMC; therefore, the MPMC reset is a fully synchronous reset. Reset should be held for a minimum of eight cycles
of the slowest PIM clock. After reset, there should not be access to any of the ports or control interfaces for 20 cycles
of the MPMC_Clk0.
DS643 February 22, 2013
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Product Specification