DS643 Datasheet, PDF (21/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
PIM I/O Signals
XCL PIM I/O Signals
Table 17: XCL PIM I/O Signals
Signal Name⁽¹⁾
Direction
FSL<Port_Num>_M_Clk
FSL<Port_Num>_M_Write
FSL<Port_Num>_M_Data
FSL<Port_Num>_M_Control
FSL<Port_Num>_M_Full
FSL<Port_Num>_S_Clk
FSL<Port_Num>_S_Read
FSL<Port_Num>_S_Data
FSL<Port_Num>_S_Control
FSL<Port_Num>_S_Exists
Input
Input
Input
Input
Output
Input
Input
Output
Output
Output
Init
Status
x
x
x
x
0
x
x
x
0
0
Description
Clock
Write enable signal indicating that data is being written to the output FSL.
Data value written to the output FSL.
Control bit value written to the output FSL signal.
Full Bit indicating output FSL FIFO is full when set.
Clock.
Read acknowledge indicating that data has been read from the input FSL.
Data value currently available at the top of the input FSL.
Control Bit value currently available at the top of the input FSL.
Flag indicating that data exists in the input FSL.
Notes:
1. When C_XCL<Port_Num>_B in use is enabled, the B port has the same signals names with an _B appended after the <Port_Num>.
PLB v4.6, SDMA_CTRL, and MPMC_CTRL PIM I/O Signals
MPMC contains Slave PLB ports for the PLB PIM, SDMA Control registers (SDMA_CTRL), and MPMC Control
register (MPMC_CTRL) interfaces. Each of these slave PLB interfaces have the same set of signal names with different
prefixes on the Port Bus Names. The <Bus_Name> prefixes are as follows:
• SDMA Control registers (SDMA_CTRL) for Ports 0 to 7: SDMA_CTRL<Port_Num>_
• SDMA_CTRL is valid if C_PIM<Port_Num>_BASETYPE = 3
• MPMC Control registers (MPMC_CTRL): MPMC_CTRL
• MPMC_CTRL is valid if PM, ECC, Debug registers, or Static PHY is enabled
• MPMC Slave PLB v4.6 PIM: SPLB<Port_Num>
• SPLB<Port_Num> is valid if C_PIM<Port_Num>_BASETYPE = 2
Table 18 lists the available signals for SDMA_CTRL, MPMC_CTRL, and PLB v4.6 PIM (SPLB). Replace <Bus_Name>
with the appropriate bus prefix.
Table 18: SDMA_CTRL, MPMC_CTRL, and PLB v4.6 (SPLB) PIM I/O Signals
Signal Name
Direction
Init
Status
Description
<Bus_Name>_Clk
Input
x
Bus clock.
<Bus_Name>_Rst
Input
x
PLB reset, active-High.
<Bus_Name>_PLB_ABus
Input
x
PLB address bus.
<Bus_Name>_PLB_PAValid
Input
x
PLB primary address valid.
<Bus_Name>_PLB_SAValid
Input
x
PLB secondary address valid.
<Bus_Name>_PLB_masterID
Input
x
PLB current master identifier.
<Bus_Name>_PLB_RNW
Input
x
PLB read not write.
<Bus_Name>_PLB_BE
Input
x
PLB byte enables.
<Bus_Name>_PLB_UABus
Input
x
PLB size of requested transfer.
DS643 February 22, 2013
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Product Specification