DS643 Datasheet, PDF (108/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 61 describes the Static PHY Interface register (SPI).
Table 61: Static PHY Interface Register (SPI)
Bit(s)
Name
Core
Access
Reset Value
Description
0:3 RDEN_DELAY
Sets the number of cycles to delay the read enable push)
R/W
C_STATIC_PHY_RDEN_
DELAY
to the read FIFOs. See Static PHY Implementation,
page 104 for more information. This value is typically 5, 6,
or 7 for DDR/DDR2 and 4, 5, or 6 for SDRAM.
4 RDDATA_CLK_SEL
Sets the read data to be re-registered on the positive or
R/W
C_STATIC_PHY_RDDATA_ ^{negative edge of MPMC_Clk0:}
CLK_SEL
1 = Positive Edge
0 = Negative Edge
5 RDDATA_SWAP_RISE
Sets the DDR read data to be shifted by 1/2 clock cycle
relative to the SDR clock:
R/W
C_STATIC_PHY_RDDATA_
SWAP_RISE
0 = no shift
1 = ½ clock cycle shift.
This register is present for DDR/DDR2 designs only.
6 UNUSED
N/A
N/A
7 FIRST_RST_DONE
R
Set to 0 during first reset to static PHY; set to 1
0
afterwards. This prevents the control register from being
reset to default values after initial reset.
8 DCM_PSEN
Set to 1 to perform one DCM phase shift increment or
R/W
0
decrement. Self Clearing.
Direction of phase shift is determined by DCM_PSINCDEC.
9 DCM_PSINCDEC
R/W
1 = perform DCM phase shift increments.
0
0 = perform DCM phase shift decrements.
Only valid with DCM_PSEN
Set to 1 when DCM phase shift increment or decrement
10 DCM_DONE
R/W
0
is complete. This bit must be cleared by MPMC.
DCM_PSEN is not set to 1 again until DCM_DONE is set
and cleared.
11 INIT_DONE
R
0
Set to 1 when initialization is complete; otherwise set to 0.
12:15 UNUSED
N/A
N/A
N/A
16:31 DCM TAP VALUE
R
A 10-bit number (sign-extended to form a 16-bit value)
which represents the status of the software-derived DCM
tap value.
The tap value is relative to the initial phase tap value set
0
in the DCM. The value of this register assumes that the
DCM PHASE_SHIFT parameter was initially set to 0;
otherwise it reports the relative phase offset only.
This value can be incorrect if the DCM phase is shifted
beyond the DCM allowable adjustment range.
DS643 February 22, 2013
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108
Product Specification