DS643 Datasheet, PDF (60/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 40 provides a summary of the available clock signals.
Table 40: Clock Summary
Signal Name
Description
MPMC_Clk0
Main MPMC clock; used to generate memory clock.
MPMC_Clk0_DIV2
MPMC_Clk0, divided by 2; used in MIG-based Virtex-5 FPGA DDR2 PHY only.
MPMC_Clk90
Main MPMC clock, phase shifted by 90 degrees. DDR/DDR2 only.
MPMC_Clk_200MHz
200 MHz clock; used in Virtex-4 and Virtex-5 architectures for IDELAY Control logic only. Only valid when
using MIG-based Virtex-4 or Virtex-5 FPGA DDR/DDR2 PHY.
MPMC_Clk_Mem
Main MPMC clock, phase-shifted by n degrees. Used with Static PHY Interface only. See Static PHY
Interface, page 103 for more details.
<PIM>_Clk
See specific PIM documentation for more details. Generally, these clocks are the same as MPMC_Clk, or
the MPMC_Clk synchronously divided by 2. The XCL, PLB, and SDMA PIMs support only 1:1 or 1:2
synchronous clock ratios. The XCL and PLB PIMs detect automatically which clock ratio is being used. The
SDMA requires that the clock ratio be specified by the C_SDMA<Port_Num>_PI2LL_CLK_RATIO
parameter.
MPMC_Rst
Main MPMC reset.
<PIM>_Rst
See specific PIM documentation for more details.
See System I/O Signals, page 16 for more information on clocks and reset signals.
Virtex-6 FPGA Clock Logic
The Virtex-6 FPGA MIG PHY requires an MMCM to be instantiated in the system separate from the MPMC. The
C_MMCM_EXT_LOC parameter is used to specify the location of the external MMCM.
When using Clock Generator core v3.02a or greater, the C_MMCM_EXT_LOC constraint is passed to the clock
generator module to generate a local constraint for itself. This parameter is derived from the MIG-generated pinout
UCF.
This external MMCM drives the MPMC_Rd_Base, MPMC_Clk_Mem, and MPMC_Clk0 clock signals.
The MPMC_DCM_PSEN, MPMC_DCM_PSINCDEC, and MPMC_DCM_PSDONE ports connect to the MMCM. This allows the
MIG PHY within MPMC to adjust the Read clock timing dynamically.
The MPMC_Clk_Rd_Base is the same frequency as MPMC_Clk_Mem, and should not be buffered to global routing.
The MPMC_Clk_Mem port drives the memory clock. MPMC_Clk0 is half the memory clock frequency and is
synchronous to MPMC_Clk_Mem. Another port called MPMC_Clk_200MHz requires a 200 MHz clock to drive the
IDELAY elements, but this clock can be asynchronous to all other clocks.
DS643 February 22, 2013
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Product Specification