DS643 Datasheet, PDF (68/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
ECC Control Register
The ECC Control register (ECCC) determines if ECC check bits are generated during memory write operation and
checked during a memory read operation. The ECCC also defines testing modes if enabled by the parameter
C_INCLUDE_ECC_TEST.
Table 43 describes the bit values for the ECCC register bits.
Table 43: ECCC Register Bit Definitions
Bit(s)
0:26
Name
Core
Access
27
FORCE_PE
R/W
28
FORCE_DE
R/W
29
FORCE_SE
R/W
30
RE
R/W
31
WE
R/W
Reset
Value
0
0
0
1⁽²⁾
1⁽²⁾
Description
Reserved
Force Parity Field Bit Error⁽¹⁾: Available for testing and determines
if parity field bit errors are forced in the data stored in the memory.
See ECC Testing for more information.
0 = No parity field bit errors are created
1 = Parity field bit errors are forced in stored data
Force Double-bit Error ⁽¹⁾: Available for testing and determines if
double-bit errors are forced in the data stored in the memory.
0 = No double-bit errors are created
1 = Double-bit errors are forced in the stored data
Force Single-bit Error⁽¹⁾: Available for testing and determines if
single-bit errors are forced in the data stored in the memory.
0 = No single-bit errors are created
1 = Single-bit errors are forced in the stored data
ECC Read Enable:
0 = ECC read logic is bypassed
1 = ECC read logic is enabled
ECC Write Enable:
0 = ECC write logic is bypassed
1 = ECC write logic is enabled
Notes:
1. This bit is available only if C_INCLUDE_ECC_TEST = 1.
2. Reset value is determined by parameter C_ECC_DEFAULT_ON.
If C_ECC_DEFAULT_ON = 1 then this bit is equal to 1
If C_ECC_DEFAULT_ON = 0, then this bit is equal to 0
DS643 February 22, 2013
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Product Specification