DS643 Datasheet, PDF (46/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
From MPMCv3 or v4 SDRAM PHYs
In MPMC5, the single-data rate SDRAM PHY was completely replaced by a Static PHY implementation, requiring
multiple manual changes.
The following minimum MHS changes are required to pass through the tools:
• Connect the MPMC_Clk_Mem port to the same clock driving the MPMC_CLK0 port.
• Set C_MPMC_CTRL_BASEADDR and C_MPMC_CTRL_HIGHADDR. It is recommended but not required that the
MPMC_CTRL bus interface be connected to the PLB bus.
• Set PARAMETER C_STATIC_PHY_RDEN_DELAY = 4 (for CAS Latency of 2).
- Increase by 1 for a registered memory.
- Increase by 1 more if the CAS Latency is 3.
• Set PARAMETER C_STATIC_PHY_RDDATA_CLK_SEL = 0. This selects the same negative edge clock capture
that was used in MPMC4.
The following additional MHS and UCF changes are suggested to take advantage of the improved read data
capture functionality of the SDRAM PHY:
• Connect MPMC_Clk_Mem to a clock driven by a DCM with the same frequency as MPMC_CLK0 but is
independently phase adjustable with respect to MPMC_CLK0.
• Connect MPMC ports to DCM to allow software control of the clock phase to port MPMC_Clk_Mem. Connect
MPMC ports MPMC_DCM_PSINCDEC, MPMC_DCM_PSEN, and MPMC_DCM_PSDONE to the corresponding ports on
the DCM driving MPMC_Clk_Mem
- Connect the MPMC_CTRL bus interface to the PLB to enable software control of the SDRAM Static PHY.
- In the UCF, add the following constraint.
- NET <MPMC Inst>*rd_data_rise_rdclk* MAXDELAY = 1000;
- Rebuild the design and use a software program to find the optimal DCM phase shift and PHY settings for
the SDRAM device and board. For a software example, see the static PHY example application in
<EDK_Install>/sw/XilinxProcessorIPLib/drivers/
mpmc_<latest version>/examples/mpmc_calibration_example.c.
From MPMCv5 Virtex-6 FPGA
Virtex-6 FPGA designs migrating from MPMC5 require multiple changes to both UCF and MHS files, which are
described in Standalone Flow: Migrating an MPMCv5 Virtex-6 FPGA Design to MPMCv6, page 96.
From MPMCv6.00.a Spartan-6 FPGA
When migrating Spartan-6 FPGA designs from MPMC v6.00.a to v6.01.a, you must choose the location of the RZQ
and ZIO pins using the C_RZQ_LOC and C_ZIO_LOC parameters. Previously, this pin selection was automatically
chosen among several possible locations, but now it is a user-selectable option supported in the MPMC IP
configuration GUI. Designs being migrated initially generate an error that the RZQ/ZIO pin selection was not made.
However, the error message displays the original pin selection choice from MPMC v6.00.a as a reference. This
information can be used to set the pinout in the MPMC IP Configuration GUI.
Note: With the ability to choose RZQ/ZIO pinout from the GUI or at the MHS level, remove any RZQ/ZIO pinout constraints in
the system.ucf file.
DS643 February 22, 2013
www.xilinx.com
46
Product Specification