DS643 Datasheet, PDF (48/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Single MicroBlaze Processor Use Case
Figure 2 shows example of a common MicroBlaze processor system layout. The MPMC module provides direct
memory access to the processor IXCL and DXCL interfaces.
A standard PLB port is defined for use with PLB devices. The MicroBlaze processor can be connected directly to the
PLB bus attached to the PLB PIM also.
X-Ref Target - Figure 2
IXCL
MicroBlaze
DXCL
IPLB DPLB
(1)
XCL
PIM
MPMC
PLB
PIM
Memory
Device
Device
PLB
ARB
x11001
Figure 2: Single MicroBlaze Processor Use Case
Note:
1. This figure shows MicroBlaze processor version 7.20 or greater using a PLB connection to the MPMC for
uncached access to memory. This approach uses a second MPMC port for the uncached access over PLB. An
alternate connection scheme is to remove the second MPMC port and use MicroBlaze processor parameters
C_ICACHE_ALWAYS_USED =1 and C_DCACHE_ALWAYS_USED = 1. These parameters cause a MicroBlaze
processor to make uncached memory accesses over XCL instead of PLB to reduce system size.
DS643 February 22, 2013
www.xilinx.com
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Product Specification