DS643 Datasheet, PDF (92/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
b. For Spartan device designs, select the top/bottom clock input location to match the location of the Global
Clock Buffer (BUFG) driving the memory clock (PORT MPMC_Clk0) in the final system design.
8. In the MIG Reserve Pins window, select any pins that you want the MIG tool not to use in its pin assignments.
Note: The Read UCF option only reads in a specially formatted file listing pins to prohibit. Consult the MIG documentation to
make sure the correct file formatting is used to reserve pins.
9. For a new pinout only: Choose New Design and click Next.
a. In the MIG Bank Selection window, select the banks to which you want to allow MIG to assign pins. You
must select enough banks to meet the required pin count totals. Click Next. Continue to step 11.
10. For existing pinout only: Choose Fixed Pin Out and click Next.
a. In the MIG Pin Selection window, choose FPGA pin locations for each MIG signal in the Pin Number
column.
Note: Excess bus width signals should be assigned to dummy locations which are later ignored.
a. Click Next when I/O location entry is complete.
11. In the MIG Summary window, review the options and click Next.
12. In the MIG Memory Model License window, mark the checkbox if memory models are desired, then click
Generate to run MIG and create the constraint files. This returns you to the MPMC GUI.
The memory simulation models created in this step are not imported by EDK and MPMC. To use these models
in an MPMC simulation, the test bench from the raw MIG project can be merged manually into the user
top-level test bench. See the Integrated MIG GUI Flow: Additional Information in the following section for the
raw MIG project location.
13. After returning to the MPMC GUI, click OK to return to XPS.
The EDK system.ucf file is not modified in the Integrated MIG flow.
14. Remove any MPMC/MIG-specific constraints in the EDK system.ucf that were added from previous flows.
See the following subsection for more detailed information about how pinout and constraint information is
handled in the Integrated MIG flow.
Integrated MIG GUI Flow: Additional Information
• The MIG project files that are generated in this flow are stored in the <EDK_Project_File>/__xps/mig. It is
very important to backup and retain these files for future use. Make sure that these files are also kept for
project archival or whenever the EDK project needs to be copied or moved.
- The raw MIG pinout and constraints information are located in
<EDK_Project_Dir>/__xps/mig/gui/*/user_design/par/*.ucf.
- The MIG UCF that is converted to have MPMC compatible instance names is located at
<EDK_Project_Dir>/__xps/mig/tmp/<MPMC Instance name>_mpmc.ucf. This becomes the core
level UCF constraints that are passed to the EDK flow.
- The core level UCF (renamed with a.ncf suffix) used by the EDK/ISE flow during ngdbuild is in
<EDK_Project_Dir>/implementation/<MPMC name>/<MPMC name>_wrapper.ncf.
- To completely clean away an old run of the MIG GUI to start the process over, remove the
<EDK_Project_Dir>/__xps/mig directory. This directory contains all the state information for the
integrated MIG flow.
- The <EDK_Project_Dir>/__xps/mig/platgen and <EDK_Project_Dir>/__xps/mig/tmp directories
contain temporary files and is regenerated during platgen. The UCF contained in the
<EDK_Project_dir>/__xps/mig/platgen directory structure does not have the chosen pinout of the
design and should be ignored.
DS643 February 22, 2013
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Product Specification