DS643 Datasheet, PDF (90/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
MIG-Based PHY Design Considerations
The following are design considerations for using the MIG-based PHY interface:
• This version of MPMC is designed to be used with MIG v3.6.1. Other MIG versions (either older or newer)
might not produce a User Constraint File (UCF) compatible with this version of MPMC. For migrating the
UCF from older MPMCv3 and MPMCv4 designs (based on MIGv1.73-MIGv3.3) to MPMC5, the following
options are available:
- The MIG v3.6.1 GUI provides an Update Design option that generates MIG v3.6.1 constraints using an older
project files from MIG v.173, v2.0, 2.1, 2.2, 2.3 or 3.0,3.1,3.2 or 3.3. If your design originally used an older MIG
version, it is strongly recommended that you use this option to update the design to make sure the correct
constraints are being used.
- Scripts and instructions are provided to migrate MPMC designs manually:
- For migration of MPMCv3 designs based on MIG v1.73 to MPMCv5. See Standalone Flow: Migrating
an MPMCv3 Design to MPMCv5, page 95 for more information.
- For migration of MPMCv4 Virtex-5 FPGA DDR2 designs to MPMCv5, see Standalone Flow: Migrating
an MPMCv4 Virtex-5 FPGA DDR2 Design to MPMCv5, page 95 for more information.
However, it is strongly recommended that the Update Design option in the MIG GUI be used instead of the
manual or scripted method. These manual or scripted methods are intended to be used to help debug the
migration of older MPMC designs only.
• When running the MIG GUI in standalone mode, ensure that the MIG memory settings match the parts you
intend to use on your custom board and also match your MPMC memory settings. In particular, ensure that
memory parameters that affect the memory interface placement like data width, number of rows, columns,
bank bits, and memory types are correct and consistent.
• Virtex-5 FPGA DDR2 boards must be designed to support differential DQS.
• It is required and extremely important to ensure that the layout and pinout of any other boards to be used with
MPMC follow the MIG design requirements.
Failure to follow MIG design rules and all applicable MIG UCF constraints could result in an inoperable
MPMC. Review all information in this section before implementing the design.
• If using ECC, ensure that the board supports a full 8-bit wide data byte lane for the ECC check bits. In previous
versions of MPMC, only 4 physical bits were used for ECC, but this version of MPMC requires the full byte
lane to be present to accommodate the PHY data calibration algorithm.
• During memory initialization (following reset), the Virtex-4, Virtex-5, and Virtex-6 FPGA MIG-based PHY
writes to the top locations in memory to set up the write training pattern. This can affect memory address
between {C_MPMC_HIGHADDR - 0xFF} and C_MPMC_HIGHADDR; therefore, after any reset, these locations in
memory are overwritten.
• Software code should not be stored in the top 0x100 address locations of memory. If using shadow memory,
review the Address Encoding, page 55 to determine which address locations are overwritten.
• In multi-rank systems, the MIG PHY only calibrates its data capture timing to one of the ranks on one of the
DIMMs. Differences in timing, process variation across memory devices, or bus loading affects across ranks
reduces timing margin and can affect the frequency range of operation.
Note: Multi-rank and multi-DIMM systems are not tested or characterized by MIG. You must ensure that the maximum
skew and signal integrity is controlled across ranks. The use of multi-rank designs is strongly discouraged. The use of
multi-DIMM designs is currently unsupported.
DS643 February 22, 2013
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Product Specification