DS643 Datasheet, PDF (35/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Spartan-3 FPGA MIG PHY Debug Registers
Table 31: Spartan-3 FPGA MIG PHY Debug Registers
Register Name
Base Address/
Offset from
C_MPMC_CTRL
BASEADDR (in hex)
S3_CALIB_REG 0x2040
S3_CALIB_
STATUS
0x2044
Bits
0:31
Field Name
Access Default
Type Value
Description
0:6 unused
7 VIO_OUT_DQS_EN
R/W
8:10 unused
11:15 VIO_OUT_DQS
R/W
16:22 unused
23 VIO_OUT_RST_DQS_DIV_EN
R/W
24:26 unused
27:31 VIO_OUT_RST_DQS_DIV
R/W
0:2 unused
3:7 DBG_DELAY_SEL
R
8:10 unused
11:15 DBG_PHASE_CNT
R
16:17 unused
18:23 DBG_CNT
R
24 unused
25 DBG_TRANS_ONEDTCT
R
26 DBG_TRANS_TWODTCT
R
27 DBG_ENB_TRANS_TWO_DTCT
R
28:31 unused
Enable signal for strobe tap selection.
0 0 = not enabled
1 = enabled
01111 Used to change the tap values for strobes.
Enable signal for RST_DQS_DIV tap
0
selection.
0 = not enabled
1 = enabled
01111
Used to change the tap values for
RST_DQS_DIV.
Tap value from the calibration logic used to
delay the strobe and RST_DQS_DIV.
Phase count gives the number of LUTs in the
clock phase.
Counter used in the calibration logic.
Asserted when the first transition is detected.
Asserted when the second transition is
detected.
Enable signal for DBG_TRANS_TWODTCT.
Related MIG PHY signal = PHY_INIT_DONE.
DS643 February 22, 2013
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Product Specification