DS643 Datasheet, PDF (51/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Transaction Ordering, Coherency, and Arbitration
Transactional coherency and arbiter features apply to both the soft and hard memory controller architectures.
Transaction Ordering and Memory Coherency
In both the hard and soft MPMC architectures, transactions are executed to memory in the order that the
transactions are acknowledged with respect to a single port; consequently, on a single port, transactions are
completed in the same order as requested.
Across multiple ports of the MPMC, there is no guarantee that the transactions issued by different ports will
complete in the request order. You can modify the arbitration algorithms so that a given port is favored over another
port. This can be used as a mechanism to influence transaction ordering but might not guarantee a specific order.
The MPMC allows write transactions to be buffered inside the MPMC. Because of the buffering, there is an
undefined time between when a write transaction has completed over NPI and when the write completes to
memory.
Because transaction ordering is not guaranteed across ports, a port doing a read from an address location being
written to by another port might read the new or the old memory value. In some applications it is important to
know that a write has completed to memory before issuing a read of that location.
There are three methods that can ensure coherency:
1. The NPI interface can monitor the Write FIFO empty flag:
- The empty flag is asserted when the write has completed to memory.
- The design can wait for the empty flag to go high before signaling that a read can be performed.
2. The design can take advantage of the fact that transactions complete in order on a given port:
- After a write to a sensitive part of memory, the device can issue a dummy read and wait for the dummy read
to complete and return data.
- The completion of the dummy read ensures that the previous write has completed to memory.
3. The arbitration algorithm can be adjusted:
- If the port performing the writes can always be set to have higher priority than the ports doing the reads, this
should also ensure that the write completes before the read across the two ports. Care should be taken with
this method if there is a possibility that the PIM can have “bubble” cycles between the write and the read
request.
Note: Using any of these methods to ensure coherency could result in reduced system performance; employ these methods
when necessary only.
The DPLB and PLB PIMs follow the PLB CoreConnect technology method for handling memory coherency (for
example, between PowerPC 405 processor instruction and data PLB interface). The PLB BUSY signal is asserted on
writes until the Write_FIFO_Empty flag is asserted indicating the write transaction has completed to memory. The
processor normally ignores the BUSY flag unless an instruction is executed such as Sync or Enforce Instruction
Execution In Order (EIEIO).
When the Sync or EIEIO instruction is executed, the processor waits for PLB BUSY to be deasserted before issuing
another transaction.
DS643 February 22, 2013
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Product Specification