DS643 Datasheet, PDF (116/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Spartan-6 FPGA Clock Logic
MCB Memory Clocking
The MCB requires some special clock circuits to properly drive the memory clock. The main clocks used by the MCB
arrive on the MPMC_Clk_Mem_2x and MPMC_Clk_Mem_2x_180 (180 degrees phase shifted clock) ports. Normally,
these clocks must be driven from the same PLL block at a frequency that is two times the memory clock; for
example, MPMC_Clk_Mem_2x running at 800 MHz for a 400 MHz memory clock.
Note: The MPMC_Clk_Mem_2x and MPMC_Clk_Mem_2x_180 signals must be driven from the PLL primitives using the
CLKOUT0 and CLKOUT1 ports of the PLL as described in UG388, Spartan-6 FPGA Memory Controller User Guide.
Also, the MPMC_MCB_DRP_Clk clock input is required. The MPMC_MCB_DRP_Clk must be driven from the same PLL
block as the MPMC_Clk_Mem_2x to ensure it is phase-aligned with MPMC_Clk_Mem_2x. The MPMC_MCB_DRP_Clk
must be between 50 and 100 MHz and be an integer-divided frequency of MPMC_Clk_Mem_2x.
Note: If the port MPMC_MCB_DRP_Clk is not connected in the MHS file, the clock is taken from MPMC_Clk0, in which case
MPMC_Clk0 must follow the same requirements of MPMC_MCB_DRP_Clk as described previously.
The following is a Microprocessor Hardware Specification (MHS) file example of how a PLL can be connected to the
MPMC.
BEGIN mpmc
.
.
.
# Connect only to PLLs LOCKED output with no intermediate logic
# except when C_MCB_USE_EXTERNAL_BUFPLL = 1
PORT MPMC_PLL_Lock = pll_module_0_LOCKED
PORT MPMC_Clk_Mem_2x = pll_module_0_CLKOUT0
PORT MPMC_Clk_Mem_2x_180 = pll_module_0_CLKOUT1
PORT MPMC_MCB_DRP_Clk = pll_module_0_CLKOUT2
END
BEGIN pll_module
PARAMETER INSTANCE = pll_module_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_CLKOUT0_DIVIDE = 1
PARAMETER C_CLKOUT1_DIVIDE = 1
PARAMETER C_CLKOUT2_DIVIDE = 8
PARAMETER C_CLKOUT1_PHASE = 180.000000
PARAMETER C_CLKFBOUT_MULT = 8
PARAMETER C_CLKFBOUT_BUF = true
PARAMETER C_CLKOUT0_BUF = false
PARAMETER C_CLKOUT1_BUF = false
PARAMETER C_CLKOUT2_BUF = true
PARAMETER C_COMPENSATION = INTERNAL
PORT CLKOUT0 = pll_module_0_CLKOUT0
PORT CLKOUT1 = pll_module_0_CLKOUT1
PORT CLKOUT2 = pll_module_0_CLKOUT2
PORT LOCKED = pll_module_0_LOCKED
PORT CLKIN1 = dcm_clk_s
PORT RST = sys_rst
PORT CLKFBOUT = pll_module_0_CLKFBOUT
PORT CLKFBIN = pll_module_0_CLKFBOUT
END
DS643 February 22, 2013
www.xilinx.com
116
Product Specification