DS643 Datasheet, PDF (112/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Spartan-6 FPGA Memory Controller Architecture
The MPMC for Spartan-6 FPGAs uses the hard Memory Controller Block (MCB) to implement core memory
controller functionality. The MCB is a dedicated embedded block that implements a multi-port memory controller
that greatly simplifies the task of interfacing Spartan-6 devices to the most popular memory standards. The MPMC
simplifies the task of connecting the MCB to many different protocol standards using Personality Interface Modules
(PIMs).
Descriptions of the PIMs, which are located in Personality Interface Modules, page 121, detail how the following
PIMs allow the MPMC to connect various interfaces to the MCB:
• Xilinx CacheLink PIM
• Soft Direct Memory Access Controller PIM for LocalLink Interfaces
• Processor Local Bus Version 4.6 PIM
• PowerPC 440 Processor Memory Controller PIM
• Video Frame Buffer Controller PIM
• Native Port Interface PIM
• MCB PIM for direct connection to the MCB user interface with no protocol translation.
Before using the MPMC, become familiar with the Spartan-6 FPGA Data Sheet and UG388, Spartan-6 FPGA Memory
Controller User Guide. These documents describe the detailed capabilities of the device and explain the board design
requirements. They can be found by following the links in Reference Documents, page 215.
DS643 February 22, 2013
www.xilinx.com
112
Product Specification