DS643 Datasheet, PDF (56/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Address Path Pipeline
The address path pipeline is controlled by C_PIM<Port_Num>_ADDRACK_PIPELINE, a per-port parameter which,
when set in the IP Configuration interface, allows the NPI address acknowledge signal to be registered. Enable this
parameter to achieve better timing, but expect one extra cycle of latency on the assertion of address acknowledge.
See IP Configuration Graphical User Interface, page 209 for more information on setting per-port parameters.
Address Alignment
When requesting a transfer at the NPI interface the PIM<Port_Num>_Addr signal has alignment restrictions on
Reads and Writes. The following subsections list the alignment restrictions by Read and Write request.
Read Requests
Addresses corresponding to a Read request must be aligned as follows:
• Word transfers (32-bit NPI only) are 4-byte aligned
• Double-word transfers (64-bit NPI only) are 8-byte aligned
• 4-word, cacheline transfers (32-bit NPI only) are 4-byte aligned
• 4-word, cacheline transfers (64-bit NPI only) are 8-byte aligned
• 8-word, cacheline transfers (32-bit NPI only) are 4-byte aligned
• 8-word, cacheline transfers (64-bit NPI only) are 8-byte aligned
• 16-word, burst transfers are 64-byte aligned
• 32-word, burst transfers are 128-byte aligned
• 64-word, burst transfers are 256-byte aligned (Not supported in all configurations. See Restrictions on 64-Word
Burst Transfers, page 173 for more information.)
DS643 February 22, 2013
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Product Specification