DS643 Datasheet, PDF (44/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
The Standalone MIG GUI Flow allows manual generation of pinouts and constraints from outside of the EDK
framework. The standalone flow not recommended because the resulting UCF requires additional modification
before use in an EDK project, and consequently is used only for existing designs, or if more control is required than
the integrated flow provides.
The Static PHY Interface lets you use designs of Virtex-4, Virtex-5, and Spartan-3 based families with pinouts that
were not designed with a MIG-compatible DDR/DDR2 pinout. The Static PHY uses a coarse DCM phase-shift to
capture DDR/DDR2 Read data. Generally, a software calibration example is used to perform the calibration.
Note: Use the Static PHY only when the MIG PHY cannot be used.
The SDRAM PHY Interface is the Static PHY modified to target Single Data-Rate (SDR) SDRAM devices in the same
FPGA families.
Choosing Memory Device Details
After you run BSB, you can choose the details of the external memory. In XPS, open the MPMC IP Configuration
GUI, and choose the appropriate memory part and memory settings which are described in Memory Interface,
page 210. For most FPGA families, you can enter an unlisted part using the CUSTOM memory part.
If you choose a different memory type, the MPMC I/O ports might need to be connected. See Memory Signals,
page 17 to determine which MPMC ports must be connected to external memory. Changing the memory type might
require clocking modifications also; see Clock Logic, page 59, Virtex-6 FPGA Clock Logic, page 60, or Spartan-6
FPGA Clock Logic, page 116 for more information.
Other memory device changes might require modification of external I/O port widths, also.
Board Considerations
When you have chosen a PHY and an created an initial system, you can determine the pinout. MIG PHY users must
follow the Memory Interface Solutions User Guide for pinout planning, pin-swapping, and board design layout rules
specific to each FPGA family and memory standard. Use the reference documents for more information on MIG
board design. A link to the MIG documentation is available in Reference Documents, page 215.
There are no specific board requirements for Static PHY and SDRAM PHY; but, because these PHYs perform global
delay adjustments only, you must reduce board skew across the entire memory interface as much as possible.
Simulation Considerations
To simulate a design using the MPMC, the user must create a test bench that connects a memory model to the
MPMC I/O signals. This is generally performed by editing the system_tb.v/.vhd test bench template file
created by the Simgen tool in XPS to add a memory model. Alternatively, the user can transfer the simulator
compile commands from Simgen into their own custom simulation/test bench environment.
Note: The MPMC does not generally support structural simulation because this is not a supported flow for the underlying MIG
PHYs. Structural simulation is therefore not recommended.
MPMC simulation should be performed in the behavioral/functional level and requires a simulator capable of
mixed-mode Verilog and VHDL language support.
It is recommended that the user place weak pull downs on all the DQ and DQS signals so that the calibration logic
can resolve logic values under simulation. Otherwise, “X” propagation of input data might cause simulation of the
calibration logic to fail.
For behavioral simulation, the MPMC_Clk and all <PIM>_Clks must also be completely phase-aligned.
DS643 February 22, 2013
www.xilinx.com
44
Product Specification