DS643 Datasheet, PDF (151/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 76: Channel Control Register
Bit(s)
Name
Core Reset
Access Value
Description
Interrupt Delay Time-out Value
0:7
IRQTimeout Read/Write
0
The maximum amount of time that an unreported packet is required to wait until
generating a Delay Interrupt (DlyIRQ) event. (Must remain unchanged for the duration
of an DMA operation.)
Interrupt Coalescing Threshold Count Value
8:15
IRQCount Read/Write
00
The number of packets that must be received to generate a Coalescing Interrupt
(ClscIrq) event. This value is loaded into the packet threshold counter when LdIrqCnt
= 1 and subsequently reloaded whenever the threshold count is reached.
16:20
Reserved
Reserved - Read as zero.
21
Use1BitCnt Read/Write
0
Use 1 Bit Wide Counters. Currently Not Used.
22
UseIntOnEnd Read/Write
Use Interrupt On End: Selects between using the interrupt-on-end mechanism or using
0
the EOP mechanism for interrupt coalescing.
1 - Selects the interrupt-on-end mechanism
0 - Selects the EOP mechanism
23
LdIRQCnt
Write
Load IRQ Count:
0
Writing a 1 to this field forces the loading of the Interrupt Coalescing counters from the
CHANNEL_CTRL.IrqCount[0:7] field. This is a self-clearing field. Read as zero
Master Interrupt Enable: When set, indicates that the DMA channel is enabled to
24
IrqEn
Read/Write
0
generate interrupts. This is the master enable for the channel. Individual sources can
be enabled and disabled separately.
25:28
Reserved
Reserved - Read as zero
29
IrqErrEn
Read/Write
0
Interrupt on Error Enable: When set, indicates that an interrupt is generated if an error
occurs
30
IrqDlyEn
Read/Write
0
Interrupt on Delay Enable: When set, indicates that an interrupt is generated when the
timeout value is reached.
31
IrqCoalEn Read/Write
0
Interrupt on Count Enable: When set, indicates that an interrupt is generated when the
interrupt coalescing threshold value is reached.
Interrupt Status Register (TX_IRQ_REG and RX_IRQ_REG)
Offsets: 0x18 and 0x38
The Interrupt Status register, one for transmit and one for receive, indicates interrupt pending and interrupt
coalescing count values. This register is used by the software application also to acknowledge pending interrupts
by writing a 1 to clear the pending interrupts. Figure 34 illustrates the Interrupt Status register, and Table 77
describes the Interrupt Status register bits.
X-Ref Target - Figure 34
Reserved
DlyCnt Reserved ErrIrq CoalIrq
0
78
15 16 17 18 19 20 21 22 23 24
28 29 30 31
DlyTmrValue
ClscCntValue
ClscCnt
Figure 34: Interrupt Status Register
DlyIrq
DS643_15_071307
Table 77: Interrupt Status Register
Bit(s)
Name
Core
Access
0:7
DlyTmrValue
Read
8:15
ClscCntrValue
Read
Reset
Value
0
FF
Description
Delay Timer Value
This field contains the real time delay timer value.
Coalesce Counter Value
This field contains the real time coalesce counter value.
DS643 February 22, 2013
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Product Specification