DS643 Datasheet, PDF (193/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
• If possible, use fixed arbitration which simplifies the arbitration logic.
• Move C_WR_TRAINING_PORT to a different port that is less timing critical (for example, using a DXCL port
instead of an SDMA port for the write training pattern).
• Run EDK in xplorer mode. This might significantly increases the tool run times but might also improve place
and route results.
MPMC Latency and Throughput
This section provides MPMC latency and throughput estimations under several MPMC configurations and
memory speeds. The values are based on using default MPMC configurations (unless otherwise noted). Actual
system performance can be affected by the timing of the memory part, PHY calibration settings, clock speeds, clock
ratios, and the exact behavior of PIMs and devices connected to the MPMC.
Latency values are provided for the initial latency of the first transaction as measured from the transaction request
at the PIM to the first data beat transferred.
Throughput values describe the theoretical maximum continuous rate of sustained data transfer using pipelined
back-to-back burst transactions from an ideal device connected to the MPMC. Throughput values might not take
into account the fraction of total available memory bandwidth taken up by refresh operations. Refresh slightly
reduces the available bandwidth of the system.
The latency and throughput values were measured under the following conditions:
1. Spartan-3 FPGA generation measurements were taken with a Spartan-3A device using MT46V32M8-75 DDR
memory or MT47H32M8-3 DDR2 memory.
2. Virtex-4 and Virtex-5 FPGA measurements were taken with a Virtex-5 device using MT46V32M8-75 DDR
memory or MT47H32M8-3 DDR2 memory. Virtex-4 FPGA performance is assumed to be similar to Virtex-5
FPGA performance.
3. Nonregistered memory was used.
4. Virtex-6 FPGA measurements are taken using an MT41J128M8XX-15E device for DDR3 and an
MT47H128M8XX-25 for DDR2. The measurements are calculated by transferring 100 KB to and from memory
and takes into account memory refresh dead time.
5. Spartan-6 FPGA measurements are taken using an MT41J128M8XX device for DDR3 and an
MT47H128M8XX-25 for DDR2. The measurements are calculated by transferring 100 KB to and from memory
and takes into account memory refresh dead time.
Note: These values are provided for guidance and are not a guarantee of performance under all conditions. Simulation and/or
hardware instrumentation (such as using ChipScope™ Pro analyzer) should be used to verify performance targets in the full
system.
DS643 February 22, 2013
www.xilinx.com
193
Product Specification