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DS643 Datasheet, PDF (16/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support
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LogiCORE IP Multi-Port Memory Controller (v6.06.a)
I/O Signals
Table 11 through Table 17 provide the I/O signals for the MPMC system, memory, and PIMs.
System I/O Signals
Table 11: System I/O Signals
Signal Name
calib_recal(3)
MPMC_Clk0
MPMC_Clk90
MPMC_Clk0_DIV2
MPMC_Clk_200MHz(1)
MPMC_Rst
MPMC_Clk_Mem(2)
MPMC_Clk_Mem_2x(3)
MPMC_Clk_Mem_2x_180(3)
MPMC_Clk_Mem_2x_CE0(3)
MPMC_Clk_Mem_2x_CE90(3)
MPMC_Clk_Mem_2x_bufpll_o(3)
MPMC_Clk_Mem_2x_180_bufpll_o(3)
MPMC_Clk_Mem_2x_CE0_bufpll_o(3)
MPMC_Clk_Mem_2x_CE90_bufpll_o
ports(3)
MPMC_PLL_Lock_bufpll_0(3)
MPMC_Clk_Rd_Base(4)
MPMC_MCB_DRP_Clk(3)
MPMC_DCM_PSEN(2)
MPMC_DCM_PSINCDEC(2)
MPMC_DCM_PSDONE(2)
MPMC_ECC_Intr
Direction
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Input
Input
Output
Output
Input
Output
Init Status
Description
Automatically
set to 0 if When asserted, starts recalibration.
unconnected
x
System clock input.
x
System clock input, phase shifted by 90 degrees. Not used with
SDRAMs or Spartan-6 FPGAs.
x
MPMC_Clk0, divided by 2, clock input.
Only valid when using MIG-based Virtex-5 FPGA DDR2 PHY.
200 MHz clock. Connects to IDELAY elements and does not have
x
to be phase or frequency related to MPMC_Clk0. Valid when using
MIG-based Virtex-4/Virtex-5/Virtex-6 FPGA PHY only.
x
System reset input. Active-High.
x
Memory read data capture clock used by static PHY or Virtex-6
FPGA memory clock; otherwise should be left unconnected.
x
MCB clock driven by a PLL block that is 2x the memory clock rate.
For example, 800 MHz for a 400 MHz memory interface.
x
MPMC_Clk_Mem_2x shifted by 180 degrees and driven from same
PLL as MPMC_Clk_Mem_2x.
I/O clock enable strobe from BUFPLL_MCB aligned to
x
MPMC_Clk_Mem_2x. Only valid if
C_MCB_USE_EXTERNAL_BUFPLL == 1.
I/O clock enable strobe from BUFPLL_MCB aligned to
x
MPMC_Clk_Mem_2x_180. Only valid if
C_MCB_USE_EXTERNAL_BUFPLL == 1.
x
Output of internal BUFPLL_MCB to enable sharing it with a
cascaded MPMC.
x
Output of internal BUFPLL_MCB to enable sharing it with a
cascaded MPMC.
x
Output of internal BUFPLL_MCB to enable sharing it with a
cascaded MPMC.
x
Output of internal BUFPLL_MCB to enable sharing it with a
cascaded MPMC.
x
Output of internal BUFPLL_MCB to enable sharing it with a
cascaded MPMC.
x
Internal Read Capture clock.
MCB DRP Clock. Must be driven from the same PLL as
x
MPMC_Clk_Mem_2x and phase aligned with MPMC_Clk_Mem_2x.
MPMC_MCB_DRP_Clk must be between 50 and 100 MHz and be
an integer-divided frequency of MPMC_Clk_Mem_2x.
x
Connects to PSEN pin of DCM to allow MPMC Static PHY to
change DCM phase.
x
Connects to PSINCDEC pin of DCM to allow MPMC Static PHY to
change DCM phase.
x
Connects to PSDONE pin of DCM to allow MPMC Static PHY to
change DCM phase.
ECC Interrupt: (level sensitive) Valid if
0
C_INCLUDE_ECC_SUPPORT is enabled.
0 = No Interrupt.
1 = Interrupt asserted.
DS643 February 22, 2013
www.xilinx.com
16
Product Specification
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