DS643 Datasheet, PDF (43/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Getting Started with the MPMC
This section provides an overview of MPMC usage, typically consisting of the following tasks, that are detailed in
subsections:
• FPGA and Memory Device Selection
• Initial Instantiation and System Assembly
• Choosing a Physical Interface
• Board Considerations
• Choosing Personality Interface Modules
• Upgrading MPMC Versions
FPGA and Memory Device Selection
Prior to using the MPMC, it is advisable to understand and evaluate its capabilities for a given application.
• For applicable FPGA and memory device support, see Table 1, page 2. This table lists the supported memory
widths.
• For MPMC clock frequency expectations, see MPMC Operational Frequencies, page 188. Some general user
clocking restrictions are also introduced in this section.
• For overall throughput estimates, see Choosing Personality Interface Modules, page 45.
Initial Instantiation and System Assembly
After you select a family and memory device you can start to create an MPMC system. The most efficient way to
create an initial system is to use the EDK XPS Base System Builder (BSB) wizard. You can invoke BSB by creating a
new XPS project. See EDK Concept Tools and Techniques (UG683) for more information on BSB and general XPS tool
usage. A link is provided in Reference Documents, page 215.
When you are using the BSB, consider choosing an existing demonstration board as the initial BSB project. While it
is possible to create a custom board through BSB, the resulting project lacks the demonstration board benefit of a
complete example UCF and hardware testing. Choose the demonstration board first by FPGA family and then by
similar memory type.
Choosing a Physical Interface
A Physical Interface layer (PHY) performs the calibration and signaling to the external memory device. For a
particular FPGA family and memory type, there could be more than one PHY choice available—see Configurable
Physical Interface for more information, specifically Table 58, page 82.
Spartan-6 FPGA designs use the Spartan-6 FPGA Memory Controller Architecture Block (MCB) as both the
memory controller and memory PHY functions of the MPMC. You perform I/O pinout selection by choosing a
MCB location using the C_MCB_LOC parameter, and then optionally choosing RZQ and ZIO pin locations, if
applicable.
Most DDR-based systems use the high-performance Memory Interface Generator PHY Interface by default. When
using a MIG PHY, you must generate a pinout from MIG and use the resulting MIG constraints as part of the
MIG/MPMC tool flow.
The EDK XPS tool manages this process, when using the integrated MIG GUI Flow, by managing the MIG UCF
constraints automatically after MIG pinout selection.
DS643 February 22, 2013
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Product Specification