DS643 Datasheet, PDF (196/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 95: NPI Latency and Throughput (Cont’d)
Number of
Ports
Pipeline
Settings
Memory Interface
NPI Width MPMC NPI
(Bits) Burst Type
Virtex-4/Virtex-5 FPGA Writes
1-8
Default
DDR2@200 MHz 32 bits
1-8
Default
DDR2@200 MHz 32 bits
1-8
Default
DDR2@200 MHz 32 bits
1-8
Default
DDR2@200 MHz 64 bits
1-8
Default
DDR2@200 MHz 64 bits
1
Default
DDR2@200 MHz 64 bits
2-8
Default
DDR2@200 MHz 64 bits
1-8
Default
DDR@100 MHz 32 bits
1-8
Default
DDR@100 MHz 32 bits
1-8
Default
DDR@100 MHz 32 bits
1-8
All Pipelines Off DDR@100 MHz 32 bits
1-8
All Pipelines Off DDR@100 MHz 32 bits
1-8
All Pipelines Off DDR@100 MHz 32 bits
Virtex-6 FPGA Writes
1-8
Default
DDR3 @ 400 MHz 32 bits
1-8
Default
DDR3 @ 400 MHz 32 bits
1-8
Default
DDR3 @ 400 MHz 32 bits
1
Default
DDR3 @ 400 MHz 32 bits
8
Default
DDR3 @ 400 MHz 32 bits
1
Default
DDR3 @ 400 MHz 32 bits
8
Default
DDR3 @ 400 MHz 32 bits
8
All Pipelines Off DDR3 @ 400 MHz 32 bits
1-8
Default
DDR3 @ 400 MHz 16 bits
1-8
Default
DDR3 @ 400 MHz 16 bits
1-8
Default
DDR2 @ 333 MHz 32 bits
1-8
Default
DDR2 @ 333 MHz 32 bits
1-8
Default
DDR2 @ 333 MHz 32 bits
Spartan-6 FPGA Writes
1
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
4
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
1
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
4
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
1
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
4
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
64
64
64
64
64
64
64
64
64
64
64
64
64
32/64
64
64
32
32
32
32
32
64
64
64
64
64
32
32
32
32
32
32
16 Word Burst
32 Word Burst
64 Word Burst
16 Word Burst
32 Word Burst
64 Word Burst
64 Word Burst
16 Word Burst
32 Word Burst
64 Word Burst
16 Word Burst
32 Word Burst
64 Word Burst
16 Word Burst
32 Word Burst
64 Word Burst
32 Word Burst
32 Word Burst
64 Word Burst
64 Word Burst
64 Word Burst
32 Word Burst
64 Word Burst
16 Word Burst
32 Word Burst
64 Word Burst
16 Word Burst
16 Word Burst
32 Word Burst
32 Word Burst
64 Word Burst
64 Word Burst
Initial
Transaction
Latency
(MPMC_Clk0)
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
Maximum Total
Data Throughput
(MB/s)
610
883
1138
753
1219
1600
1766
400
533
640
400
533
640
700
1143
1676
800
1145
801
1677
1677
839
1094
615
996
1442
400
639
400
908
356
1143
DS643 February 22, 2013
www.xilinx.com
196
Product Specification