DS643 Datasheet, PDF (53/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Soft Memory Controller Architecture
The MPMC uses a soft (FPGA logic-based) memory controller for Spartan-3, Virtex-4, Virtex-5, and Virtex-6
architectures. The MPMC soft FPGA logic-based architecture comprises the following components:
• Address Path
• Data Path
• Clock Logic
• Spartan-3, Virtex-4, and Virtex-5 FPGA Reset Logic
• Error Correction Code (optional)
• Performance Monitoring (optional)
• Configurable Physical Interface
• Descriptions of the Personality Interface Module (PIM) Parameters, page 13, (PIMs) which are available in the
soft memory controller, detail how the PIMs allow MPMC to connect to various interfaces. The available PIMs
are:
- Xilinx CacheLink PIM
- Soft Direct Memory Access Controller PIM for LocalLink Interfaces
- Processor Local Bus Version 4.6 PIM
- PowerPC 440 Processor Memory Controller PIM
- Video Frame Buffer Controller PIM
- Native Port Interface PIM
- MCB PIM
Throughout this document, the term “word” signifies a 32-bit word.
Figure 4 is a block diagram of the MPMC soft memory controller architecture. The following subsections describe
the MPMC soft memory controller architectural features.
DS643 February 22, 2013
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Product Specification