DS643 Datasheet, PDF (181/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
8-Word, Cacheline Write with Almost Full Flag Asserted
Figure 50 shows the following:
• A 64-bit NPI.
• An 8-word, cacheline Write transfer.
• The WrFIFO_AlmostFull is asserted on same cycle as the third WrFIFO_Push. The fourth WrFIFO_Push and
AddrReq are delayed until after WrFIFO_AlmostFull is deasserted.
• The address is acknowledged in the same cycle as it is requested.
• The address is on an 8-word boundary.
• The RdModWr does not need to be asserted because WrFIFO_BE is 0xFF during WrFIFO_Push, and because an
8-word transfer is larger than maximum value of 4*C_MEM_DATA_WIDTH.
• The Write Transfer Safe Mode is used (AddrReq is asserted on same cycle as the last WrFIFO_push.)
X-Ref Target - Figure 50
MPMC_CLK0
AddrReq
AddrAck
Addr[31:0]
0x20
RNW
Size[3:0]
0x2
RdModWr
InitDone
WrFIFO_Empty
WrFIFO_AlmostFull
WrFIFO_Push
WrFIFO_Flush
WrFIFO_Data[63:0]
D0
D1
D2
D3
WrFIFO_BE[7:0]
0xFF
Figure 50: 64-bit NPI 8-Word Cache-line Write with Almost Full Flag Asserted
DS643_43_072407
DS643 February 22, 2013
www.xilinx.com
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Product Specification