DS643 Datasheet, PDF (74/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Performance Monitoring
The MPMC Performance Monitor (PM) is an optional per-port feature that counts transaction lengths across each
NPI interface, and is supported on Spartan-3, Spartan-6, Virtex-4, Virtex-5, and Virtex-6 FPGAs. The PM provides
the ability to instrument and measure the performance of the MPMC by collecting transactional statistics at the NPI
level relative to the memory clock rate. Each PM is capable of capturing the duration, size, read or write, and dead
cycle counts of each transaction. These are stored into a block RAM and are retrievable over the MPMC_CTRL Slave
PLB v.46 interface. PM cycle counts only represent transactions across the NPI interface and do not include latency
of attached PIMs or user NPI logic.
The following subsections describe the PM:
• PM Features
• Performance Monitor Operation
• Performance Monitor Measurement Methodology
• Performance Monitoring Usage Example
• Performance Monitor Registers
PM Features
The PM provides:
• An optional configurable length global cycle counter.
• An optional configurable length arbitration dead cycle counter for each port.
• The MPMC_CTRL Slave PLB v4.6 interface to control and collect data from the Performance Monitors.
• A performance monitor state machine and data collector consuming one block RAM per port enabled.
• PM registers.
Performance Monitor Operation
The following subsections provide an outline of the PM measurement methodology and give an example of the
steps in a PM monitoring session.
Performance Monitor Measurement Methodology
The cycle counts recorded in each data bin is recorded as following:
• Data Bin Read Transactions: Number of memory clock cycles from NPI_<PortNum>AddrReq until last data is
popped from data FIFO.
• Data Bin Write Transactions: Number of memory clock cycles from NPI_<PortNum>AddrReq until the later of
NPI_<PortNum>AddrAck or the last push into the data FIFO.
• Global Cycle Counter: Counts each memory clock cycle after at least one PM is enabled.
• Dead Cycle Counter: Counts the number of memory cycles from NPI_<PortNum>AddrReq until granted by
NPI_<PortNum>AddrAck.
DS643 February 22, 2013
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Product Specification