DS643 Datasheet, PDF (98/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
To verify that the tap delay circuit, “cal_ctl” AREA_GROUP, and BUFG driving the memory clock are all placed
correctly, follow these steps:
1. Open the Post-PAR design.ncd and design.pcf files in the FPGA Editor.
2. Select Routed Nets from the List window located at the top left-hand side. This shows all the routed net names
of the design.
3. Enter *tap_dly*/tap* in the Name Filter window to select the tap_dly chain, and click the Apply button on
the right-hand side of the Name Filter window.
The displayed nets are now selected in the Array Window.
4. Zoom into the area in the Array window where the selected routes are highlighted.
5. If the tap delay circuit is properly constrained, the logic is located in a single column in four sequential
Configurable Logic Blocks (CLBs). This indicates the RLOC_ORIGIN is correct.
Figure 10 is a screen capture showing an example of the correct placement of the tap_dly circuits.
X-Ref Target - Figure 10
Figure 10: Correct Placement of tap_dly Circuits
6. Repeat steps 3, 4, and 5 using cal_ctl in the Name Filter window. If the cal_ctl circuit is properly
constrained, the logic is placed in the area near the tap delay circuit on the same side of the device.
7. Find the global clock buffer (BUFG) driving the clock to the MPMC_Clk0 port.
8. Go back to the List window, select All Components and sort the List window by Type. Find the BUFGMUX
components in the Type column. Select the named BUFG that is driving the MPMC_Clk0 port and verify it is
located close to the tap delay circuit (on the same side of the device).
DS643 February 22, 2013
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Product Specification