DS643 Datasheet, PDF (76/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Performance Monitor Control Register
The Performance Monitor Control register (PMCTRL) sets the enable bits for performance monitors to capture
statistics and place them in the data bins. Initially, the performance monitors are not enabled and the data bins are
initialized to 0.
The performance monitor enable bit should be set to 0 when reading back data to maintain consistent data across all
the data bins. Setting the performance monitor enable bit to 1 immediately starts capturing data and also enables
the dead cycle counters, if the parameter is enabled.
If the global cycle counter is enabled, it counts when any of the enable bits are 1. Table 52 describes the PMCTRL
register bits.
Table 52: PMCTRL Register Bit Definitions
Bit(s)
Name
Core Access
Reset
Value
Description
0
PM0_ENABLE
R/W
0
1 = Enable PM0
0 = Disable PM0
1
PM1_ENABLE
R/W
0
1 = Enable PM1
0 = Disable PM1
2
PM2_ENABLE
R/W
0
1 = Enable PM2
0 = Disable PM2
3
PM3_ENABLE
R/W
0
1 = Enable PM3
0 = Disable PM3
4
PM4_ENABLE
R/W
0
1 = Enable PM4
0 = Disable PM4
5
PM5_ENABLE
R/W
0
1 = Enable PM5
0 = Disable PM5
6
PM6_ENABLE
R/W
0
1 = Enable PM6
0 = Disable PM6
7
PM7_ENABLE
R/W
0
1 = Enable PM7
0 = Disable PM7
8:14
Reserved
Reserved
15
PM_GC_CLR
W
X
1 = Clear Global Cycle Counter
0 = No Action
16
PM0_DCC_CLR
W
X
1 = Clear Dead Cycle Counter PM0
0 = No Action
17
PM1_DCC_CLR
W
X
1 = Clear Dead Cycle Counter PM1
0 = No Action
18
PM2_DCC_CLR|
W
X
1 = Clear Dead Cycle Counter PM2
0 = No Action
19
PM3_DCC_CLR
W
X
1 = Clear Dead Cycle Counter PM3
0 = No Action
20
|PM4_DCC_CLR
W
X
1 = Clear Dead Cycle Counter PM4
0 = No Action
21
PM5_DCC_CLR
W
X
1 = Clear Dead Cycle Counter PM5
0 = No Action
22
PM6_DCC_CLR|
W
X
1 = Clear Dead Cycle Counter PM6
0 = No Action
23
PM7_DCC_CLR
W
X
1 = Clear Dead Cycle Counter PM7
0 = No Action
24-31
Reserved
Reserved
DS643 February 22, 2013
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76
Product Specification