DS643 Datasheet, PDF (30/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Parameter and I/O Signal Dependencies
Table 24 lists the MPMC parameter and I/O signal dependencies.
Table 24: MPMC Dependencies
Parameter Name
C_DDR2_DQSN_ENABLE
C_FAMILY
C_FAMILY
C_FAMILY
C_MEM_TYPE
C_FAMILY
C_USE_STATIC_PHY
C_MEM_TYPE
C_FAMILY
C_USE_STATIC_PHY
C_MEM_TYPE
C_FAMILY
C_USE_STATIC_PHY
C_MEM_TYPE
C_MEM_ADDR_WIDTH
C_MEM_BANKADDR_WIDTH
C_MEM_CE_WIDTH
C_MEM_CLK_WIDTH
C_MEM_CS_N_WIDTH
C_MEM_DATA_WIDTH
C_ECC_DATA_WIDTH
Affects Signal
DDR2_DQS_n
selfrefresh_enter
selfrefresh_mode
calib_recal
MPMC_PLL_Lock
MPMC_Clk_Mem_2x
MPMC_Clk_Mem_2x_180
MPMC_Clk_Mem_2x_CE0
MPMC_Clk_Mem_2x_CE90
MPMC_Clk_Rd_Base
SDRAM_*
DDR_*
DDR2_*
DDR3_*
mcbx_*
MPMC_Clk_Mem
MPMC_DCM_PSEN
MPMC_DCM_PSINC_DEC
MPMC_DCM_PS_DONE
MPMC_Clk0_DIV2
MPMC_Clk_200MHz
MPMC_Idelayctrl_Rdy_I
MPMC_Idelayctrl_Rdy_O
mcbx_dram_addr
DDR3_Addr
DDR2_Addr
DDR_Addr
SDRAM_Addr
mcbx_dram_ba
DDR3_BankAddr
DDR2_BankAddr
DDR_BankAddr
SDRAM_BankAddr
DDR3_CE
DDR2_CE
DDR_CE
SDRAM_CE
DDR3_Clk
DDR3_Clk_n
DDR2_Clk
DDR2_Clk_n
DDR_Clk
DDR_Clk_n
SDRAM_Clk
DDR3_CS_n
DDR2_CS_n
DDR_CS_n
SDRAM_CS_n
mcbx_dram_dq
DDR3_DQ
DDR2_DQ
DDR_DQ
SDRAM_DQ
Relationship Description
Controls visibility of the differential DQS_n signal.
Spartan-6 FPGAs only.
Virtex-6 FPGAs only.
Only one set of these ports are available depending on
C_MEM_TYPE setting.
Signals are available only if C_USE_STATIC_PHY =1 or
if using Virtex-6 FPGAs or SDRAMs.
This signal is available only when C_FAMILY is virtex5,
C_USE_STATIC_PHY is 0 and C_MEM_TYPE is DDR2.
These signals are available if C_FAMILY is virtex4,
C_USE_STATIC_PHY is 0, and C_MEM_TYPE is not
SDRAM.
Width of address to memory.
Width of bank address to memory.
Number of clock enable outputs.
Number of clock/inverted/clock pair outputs.
Number of chip select outputs.
Width of data at memory interface.
DS643 February 22, 2013
www.xilinx.com
30
Product Specification