DS643 Datasheet, PDF (110/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
SDRAM PHY Interface
The SDRAM PHY is the interface between the SDRAM and the MPMC control path, address path, and datapath.
The interface supports Virtex-4, Virtex-5 and Spartan-3/3A/3E/3AN/3A DSP devices. The SDRAM PHY uses the
DCM phase adjustment based read data capture scheme used for the Static PHY. See the Static PHY Interface,
page 103 for required details of the SDRAM PHY, including timing constraints, board design, and software
calibration considerations. Additional usage information and an example system is available from Xilinx Answer
38476 at://www.xilinx.com/support/answers/38476.htm.
The following subsections describe the SDRAM PHY interface:
• SDRAM PHY Features
• Low Frequency SDRAM Clock and DCM Phase Adjustment Limits
• Connecting Memory to the PHY Interface
• Connecting Memory to a DDR2 MPMC Design Example
SDRAM PHY Features
The SDRAM PHY includes the following supported features:
• Column Access Strobe (CAS) latencies of 2, 2.5, and 3
• SDRAM data widths of 8, 16, 32, and 64
• DIMMs (both registered and unregistered)
• Multiple Memory Ranks
• ECC support
The PHY interface works from MPMC_Clk0, which issues the control, data, and address signals to memory. To clock
SDRAM, the PHY uses an inverted version of MPMC_Clk0. This gives a 1/2 clock period setup and hold time for
memory control and address signals.
To drive the data bus with valid Read data, the memory requirement is CAS_LATENCY – 1 + Tac time (Access Time)
after registering the read command. Figure 12 illustrates the SDRAM Read data timing.
X-Ref Target - Figure 12
T0
CLK
T1
T2
T3
COMMAND
DQ
READ
NOP
tLZ
tAC
NOP
tOH
DOUT
CL = 2
Figure 12: SDRAM Read Data Timing
DS643_06_071307
DS643 February 22, 2013
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Product Specification