DS643 Datasheet, PDF (122/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
XCL Features
The XCL PIM supports the following features:
• 1-, 4-, 8- and 16-word reads and writes.
• Auto-detection (at reset) for clock ratios of 2:1 and 1:1 of NPI (the MPMC Memory Clock) to XCL.
• Read-only optimizations.
• 32-bit XCL data width and 32-bit NPI data width.
• 32-bit address offset (the optional address offset is added to the XCL transaction address to compute the
physical memory address to be accessed.)
• Auto-detection of MicroBlaze processor parameters.
• Optimized state machine and datapaths when connected to MicroBlaze processor.
• Configurable pipeline stages for latency versus frequency optimizations.
• Support for two XCL buses connected to one NPI port. The design allows for connecting MicroBlaze processor
D-side and I-side XCL to a single NPI port for reduced resources with minimal performance hit.
• Target word first reads (except in the case of the DXCL2 and IXCL2 SUBTYPES.)
XCL Overview
The Xilinx CacheLink (XCL) PIM is highly optimized and configurable that allows you to connect a MicroBlaze
processor XCL bus interface to SDRAM, DDR, and DDR2 memories with MPMC.
The XCL PIM translates XCL commands to NPI transactions to perform reads and writes to memory. Each XCL PIM
instantiation connects to MPMC NPI using a 32-bit datapath. The XCL bus interface supports fixed burst size reads
and either fixed burst writes, or word, half-word, byte transaction sizes. The XCL signaling is a simple FIFO-style
interface based on the FSL bus interface protocol.
Transactions are initiated by the master by pushing commands into the XCL PIM. If the operation is a write, then
the master also pushes the correct number of data beats into the FIFO immediately following the write command.
If the operation is a read, then the data will be returned by another FSL channel where the data is popped out of the
FIFO-style interface.
Figure 14 is a block diagram of the NPI to XCL translation using a MicroBlaze processor.
X-Ref Target - Figure 14
NPI
XCL
NPI Signals
Combinatorial
Logic
FIFO
FIFO
Access FSL Signals
Read Data FSL Signals
DS643_52_071307
Figure 14: MicroBlaze Processor XCL Block Diagram
DS643 February 22, 2013
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Product Specification