DS643 Datasheet, PDF (79/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Dead cycles typically occur due to the MPMC controller processing older or higher priority port accesses or the
memory being unavailable during external memory maintenance.
Performance Monitor Data Bin Registers
The Performance Monitor Data Bin registers (PMx_DATA_BINx) contain the transaction information for the
performance monitors. Each performance monitor contains 512 36-bit data bins. These values are read-only 36-bit
registers that are padded with zeros on the left to expand them to 64 bits. Therefore, each performance monitor data
bin is 8 kb of data.
Each bin contains a count of transactions for a specific PM port, the NPI transaction type, the transaction direction,
and the exact number or range of clock cycles elapsed. For example, one data bin on PIM port 2 might contain the
total quantity of 32-word burst-type Write transactions which lasted between 8 and 15 clock cycles because the PM
was first enabled.
Data Bin Organization
Each PM is divided into eight qualifiers, indicating the transaction size. These qualifiers are then subdivided into
Writes and Reads. This allows 32 bins per qualifier each write and read. The bins themselves represent the
transaction length of that particular qualifier. The 36-bit number the bin contains represents how many times that
transaction length has been counted.
Qualifier Definitions
Table 55 describes the qualifier definitions.
Table 55: Qualifier Definitions
Qualifier
0
1
2
3
4
5
6
7
Description
Byte – Double Words
Cache Line 4
Cache Line 8
Burst 16
Burst 32
Burst 64
Reserved
Reserved
DS643 February 22, 2013
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Product Specification