DS643 Datasheet, PDF (19/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 14: DDR2 I/O Signals (Cont’d)
Signal Name⁽¹⁾
Direction
DDR2_WE_n
Output
Init Status
1
Command input.
Description
Notes:
1. For detailed signal descriptions, see device-specific data sheets.
2. Required when using MIG-based Spartan-3/3A/3AN/3A DSP/3E DDR/DDR2 PHY.
3. The MHS signal connecting this port and the MHS external port must have the same name. See
www.xilinx.com/support/answers/14264.htm. Reference Documents, page 215 has a link to this topic.
4. Required when differential DQS is enabled (C_DDR2_DQSN_ENABLE = 1).
DDR3 I/O Signals (Virtex-6 FPGAs Only)
Table 15: DDR3 I/O Signals
Signal Name⁽¹⁾
DDR3_Addr
DDR3_BankAddr
DDR3_CAS_n
DDR3_CE
DDR3_CS_n
DDR3_Clk
DDR3_Clk_n
DDR3_DM
DDR3_DQ⁽²⁾
DDR3_DQS⁽²⁾
DDR3_DQS_n⁽³⁾
Direction
Output
Output
Output
Output
Output
Output
Output
Output
In/Out
In/Out
In/Out
DDR3_ODT
Output
DDR3_RAS_n
DDR3_Reset_n
DDR3_WE_n
Output
Output
Output
Init Status
x
x
1
0
1
0
1
x
x
x
x
0
1
1
1
Description
Row/Column address.
Bank address.
Command input.
1 = Clock enabled.
0 = Chip select enabled.
Clock to memory.
Inverted clock to memory.
Data mask outputs.
Data.
Data Strobe.
Inverted Data Strobe.
On-Die-Termination signal. Care must be taken when connecting
these pins to your memory when you have more than one rank; there
is a direct relationship to the DDR3_CS_n pins.
Command input.
Inverted reset.
Command input.
Notes:
1. For detailed signal descriptions, see to device-specific data sheets.
2. The MHS signal connecting this port and the MHS external port must have the same name. See
www.xilinx.com/support/answers/14264.htm. Reference Documents, page 215 has a link to this topic.
3. Required when differential DQS is enabled (C_DDR3_DQSN_ENABLE = 1).
DS643 February 22, 2013
www.xilinx.com
19
Product Specification