English
Language : 

DS643 Datasheet, PDF (123/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support
LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Connecting XCL to a MicroBlaze Processor
When connecting the MicroBlaze processor IXCL and DXCL buses to the MPMC XCL PIM, the tools automatically
optimize the configuration and set many of the parameters. Table 66 lists the automatically configured parameters
and their values when connected to a MicroBlaze processor.
Table 66: Auto-Computed Parameter Values Inherited from MicroBlaze Processor Bus Connections
MPMC Parameter Name
Auto-computed
MPMC Parameter
Value
MicroBlaze Processor
Bus Interface Name
MicroBlaze Processor
Parameter Settings
C_PIM<Port_Num>_SUBTYPE
C_XCL<Port_Num>_LINESIZE
C_XCL<Port_Num>_WRITEXFER
IXCL
IXCL2
DXCL
DXCL2
4
8
4
8
0
1
IXCL
IXCL
DXCL
DXCL
IXCL
IXCL
DXCL
DXCL
IXCL
DXCL
Notes:
1. Not available in MicroBlaze processor versions earlier than v7.20a.
C_ICACHE_INTERFACE = 0
C_ICACHE_INTERFACE = 1(1)
C_DCACHE_INTERFACE = 0
C_DCACHE_INTERFACE = 1(1)
C_ICACHE_LINESIZE = 4
C_ICACHE_LINESIZE = 8
C_DCACHE_LINESIZE = 4
C_DCACHE_LINESIZE = 8
None
None
Typical MicroBlaze processor transfers over the XCL PIM consists 4- or 8-word reads (determined at synthesis) and
single word, halfword, or byte writes (if using a data-side channel.) When connected to a MicroBlaze processor
Version 7.20.a or greater and the MicroBlaze processor parameter C_DCACHE_INTERFACE = 1, the XCL PIM also
supports cache-line writes of either 4 or 8 words. The memory to XCL and by extension MicroBlaze processor clock
frequency can either be 1:1 or 2:1 and is auto-detecting. The XCL PIM contains minimal buffering and pipeline
stages that can be configured for low resource utilization, and provides support for high frequencies. The XCL PIM
with the addition of the B port (see Dual XCL Buses on One XCL PIM) supports connecting two XCL buses to one
MPMC Port. This provides lower utilization of resources with minimal impact on performance when connecting
instruction-side XCL and data-side XCL MicroBlaze processor buses to the MPMC.
DS643 February 22, 2013
www.xilinx.com
123
Product Specification