DS643 Datasheet, PDF (14/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
PLB v4.6 PIM Design Parameters
Table 6 lists the PLB PIM design parameters.
Table 6: PLB v4.6 PIM Design Parameters
Parameter Name
C_SPLB<Port_Num>_AWIDTH^(2),(3)
C_SPLB<Port_Num>_DWIDTH^(2),(3)
Default
Value
32
64
C_SPLB<Port_Num>_NATIVE_DWIDTH⁽²⁾
64
C_SPLB<Port_Num>_PLB_NUM_MASTERS^(2),(3)
1
C_SPLB<Port_Num>_PLB_MID_WIDTH^(1),(2),(3)
1
C_SPLB<Port_Num>_P2P^(2),(3)
1
C_SPLB<Port_Num>_SUPPORT_BURSTS^(2),(3)
0
C_SPLB<Port_Num>_SMALLEST_MASTER^(2),(3)
32
Allowable
Values
32
32,64,128
32,64
1-16
0- 4
0,1
0,1
32,64,128
Description
PLB Least Significant Address Bus Width.
Width of the PLB Data Bus.
Width of the PIM Internal Data Bus. This is set automatically
for Spartan-6 FPGA designs based on the width of the
corresponding MCB port.
Number of masters that can be connected the PIM.
PLB Master ID Bus Width.
The value is log₂
(C_SPLB<Port_Num>_PLB_NUM_MASTERS) with a
minimum value of 1.
Selects Shared Bus or Point-to-Point (P2P) configuration for
the PLB slave port:
0 = PLB Shared Bus Connection.
1 = PLB P2P Connection.
Must be set to 1 when C_PIM<Port_Num>_SUBTYPE is set
to IPLB or DPLB.
PLB PIM Burst Support:
0 = Single Word transactions.
1 = Single, cache line, and burst transactions.
Width of the smallest Master Data Bus.
Notes:
1. log₂ represents a logarithm function of base 2. For example, log₂(1)=0, log₂(2)=1, log₂(4)=2, log₂(8)=3, log₂(16)=4.
2. Valid if C_PIM<Port_Num>_BASETYPE = 2 (SPLB)
3. These parameters are normally calculated by the XPS based on what devices are connected to the PLB bus.
SDMA PIM Design Parameters
Table 7 lists the SDMA PIM design parameters.
Table 7: SDMA PIM Design Parameters
Parameter Name
C_SDMA_CTRL_BASEADDR^(1),(2)
C_SDMA_CTRL_HIGHADDR^(1),(2)
C_SDMA_CTRL<Port_Num>_BASEADDR^(1),(2)
C_SDMA_CTRL<Port_Num>_HIGHADDR^(1),(2)
C_SDMA_CTRL<Port_Num>_AWIDTH^(1),(3)
C_SDMA_CTRL<Port_Num>_DWIDTH^(1),(3)
C_SDMA_CTRL<Port_Num>_NATIVE_DWIDTH^(1),(3)
C_SDMA_CTRL<Port_Num>_PLB_NUM_MASTERS^(1),(3)
C_SDMA_CTRL<Port_Num>_PLB_MID_WIDTH^(1),(3)
C_SDMA_CTRL<Port_Num>_P2P^(1),(3)
C_SDMA_CTRL<Port_Num>_SUPPORT_BURSTS^(1),(3)
C_SDMA_CTRL<Port_Num>_SMALLEST_MASTER^(1),(3)
Default Value
0xFFFFFFFF
0x00000000
0xFFFFFFFF
0x00000000
32
64
32
1
1
1
0
32
Allowable
Values
Description
Valid Address
SDMA CTRL Shared PLB v4.6 Base
Address.
Valid Address
SDMA CTRL Shared PLB v4.6 High
Address.
Valid Address SDMA CTRL PLB Base Address.
Valid Address SDMA CTRL PLB High Address.
32
PLB Address Width.
32,64,128 PLB Data Width.
32
PLB Native Data Width.
0-16
PLB Number of masters on the Bus.
0-4
PLB Master ID Width.
PLB Point-to-Point (P2P) support:
0,1
0 = Not Supported.
1 = Supported.
PLB PIM Burst support:
0
0 = Not Supported.
1 = Supported.
32,64,128 PLB Smallest Master on Bus.
DS643 February 22, 2013
www.xilinx.com
14
Product Specification