DS643 Datasheet, PDF (41/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 35: MCSR0 Bit Definitions (Cont’d)
Bit(s)
Field Name
Core Default
Access Value
Description
20:23
Memory Width (not
including ECC Data Bits)
R
External Memory Interface Width:
0x3 = 8 bits
x
0x4 = 16 bits
0x5 = 32 bits
0x6 = 64 bits
24
Reserved
R
x
Reserved
25:27 Number of Ports
Number of Ports:
0x0 = 1 port
0x1 = 2 port
0x2 = 3 ports
R
x
0x3 = 4 ports
0x4 = 5 ports
0x5 = 6 ports
0x6 = 7 Ports
0x7 = 8 ports
28:31 Device Family
Device Family:
0x0 = Spartan-3
R
x
0x1 = Virtex-4
0x2 = Virtex-5
0xF = Unknown Family
Performance Monitor Register Summary
These registers are available only when a Performance Monitor (PM) is enabled. See Performance Monitor
Registers, page 75 for detailed Performance Monitor register information.
Table 36: Performance Monitor Register Summary
MPMC_CTRL
Base Address + Offset (hex)
Register Name
Access
Type
Default Value (hex)
Description
PM CONTROL
C_MPMC_CTRL_BASEADDR + 0x7000 PMCTRL
R/W
00000000
PM Control Register.
C_MPMC_CTRL_BASEADDR + 0x7004 PMCLR
W
00000000
PM Clear Register.
C_MPMC_CTRL_BASEADDR + 0x7008 PMSTATUS
R/TOW
00000000
PM Status Register.
PM DATA
C_MPMC_CTRL_BASEADDR + 0x7010
C_MPMC_CTRL_BASEADDR + 0x7020
C_MPMC_CTRL_BASEADDR + 0x7028
PMGCC
PM0_DCC
PM1_DCC
R
0000000000000000⁽¹⁾ PM Global Cycle Counter.
R
0000000000000000⁽²⁾ PM Dead Cycle Counter Port 0.
R
0000000000000000⁽²⁾ PM Dead Cycle Counter Port 1.
C_MPMC_CTRL_BASEADDR + 0x7030 –
C_MPMC_CTRL_BASEADDR + 0x7050
C_MPMC_CTRL_BASEADDR + 0x7058
C_MPMC_CTRL_BASEADDR + 0x8000
C_MPMC_CTRL_BASEADDR + 0x8008
PM2_DCC –
PM6_DCC
PM7_DCC
PM0_DATABIN0
PM0_DATABIN1
R
0000000000000000⁽²⁾ PM Dead Cycle Counter Port 2-6.
R
0000000000000000⁽²⁾ PM Dead Cycle Counter Port 7.
R
0000000000000000⁽³⁾ PM Port 0, Data Bin 0.
R
0000000000000000⁽³⁾ PM Port 0, Data Bin 1,
C_MPMC_CTRL_BASEADDR + 0x8010 - PM0_DATABIN2 –
C_MPMC_CTRL_BASEADDR + 0x8FF8 PM0_DATABIN511
R
0000000000000000⁽³⁾
PM Port 0, Data Bin 2.
PM Port 0, Data Bin 511,
C_MPMC_CTRL_BASEADDR + 0x9000 - PM1_DATABIN0 –
C_MPMC_CTRL_BASEADDR + 0xFFF8 PM7_DATABIN511
R
0000000000000000⁽³⁾
PM Port 1, Data Bin 0.
PM Port 7, Data Bin 511.
Notes:
1. The size of this register is 64 bits and is determined by the C_PM_GC_WIDTH parameter. If this parameter is less than 64 bits, the MSB is
padded with 0s.
2. The sizes of these registers are 64 bits and are determined by the C_PM_DC_WIDTH parameter. If this parameter is less than 64 bits, the
MSB is padded with 0s.
3. The size of this register is 64 bits, the data bins only hold 36 bins, therefore the upper MSBs are padded with 0s.
DS643 February 22, 2013
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Product Specification