DS643 Datasheet, PDF (187/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
8-Word, Cacheline Read
Figure 56 shows the following:
• A 32-bit NPI.
• An 8-word cacheline Read transfer.
• The address is acknowledged in the same cycle as it is requested.
• The address is on a word boundary.
• The RdFIFO_RdWdAddr indicates that data is returned target-word first.
• RdFIFO_Latency values.
X-Ref Target - Figure 56
MPMC_CLK0
AddrReq
AddrAck
Addr[31:0]
0x4
RNW
Size[3:0]
0x2
RdModWr
InitDone
RdFIFO_Empty
RdFIFO_Pop
RdFIFO_Flush
RdFIFO_Latency[1:0]
RdFIFO_Data[31:0]
RdFIFO_RdWdAddr[3:0]
0x0
D0
D1
D2
D3
D4
D5
D6
D7
0x1 0x2
0x3 0x4 0x5
0x6 0x7
0x0
Case 1
RdFIFO_Latency[1:0]
RdFIFO_Data[31:0]
RdFIFO_RdWdAddr[3:0]
RdFIFO_Latency[1:0]
RdFIFO_Data[31:0]
RdFIFO_RdWdAddr[3:0]
0x1
D0
D1
D2
D3
D4
D5
D6
D7
0x1 0x2
0x3 0x4
0x5
0x6 0x7
0x0
0x2
D0
D1
D2
D3
D4
D5
D6
D7
0x1 0x2
0x3 0x4
0x5
0x6 0x7
0x0
Case 2
Case 3
X11007
Figure 56: 32-Bit NPI 8-Word Cacheline Read
MCB PIM
The MCB PIM permits direct connection to the MCB user ports. The MCB configuration (data width and direction)
is defined by the C_PORT_CONFIG parameter.
For information about the MCB port protocol and configuration, see the Spartan-6 FPGA Memory Controller
Architecture, page 112 and the Spartan-6 FPGA Memory Controller User Guide. Reference Documents, page 215
contains a link to this document.
DS643 February 22, 2013
www.xilinx.com
187
Product Specification