DS643 Datasheet, PDF (152/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 77: Interrupt Status Register (Cont’d)
Bit(s)
Name
Core
Access
Reset
Value
16:17
Reserved
18:21
ClscCnt
Read
0
22:23
24:28
29
DlyCnt
Read
0
Reserved
ErrIrq
Read/Write
0
30
DlyIrq
Read/Write
0
31
Coallrq
Read/Write
0
Description
Reserved - read as zero.
Coalesce Interrupt Count
Indicates the number of events due to reaching the interrupt coalesce
threshold.
Delay Interrupt Count
Indicates the number of events due to reaching the wait bound delay time.
Reserved - read as zero
Error Interrupt Event
Indicates that an error has occurred. Writing a 1 to this bit clears the
interrupt.
Delay Interrupt Event
Indicates that delay timeout event has occurred. Writing a 1 to this bit
clears the interrupt.
Coalesce Interrupt Event
Indicates that an interrupt event threshold count has been reached. Writing
a 1 to this bit clears the interrupt.
Channel Status Register (TX_CHNL_STS and RX_CHNL_STS)
Offsets: 0x1C and 0x3C
The Channel Status register, one for transmit and one for receive, contains status for a particular channel. Figure 35
illustrates the Channel Status register, and Table 78 describes the Channel Status register bits.
X-Ref Target - Figure 35
Reserved
NxtPErr
CmpErr
BsyWr
Reserved
IOE Cmplt EOP Rsvd
0
9 10 11 12 13 14 15 16
23 24 25 26 27 28 29 30 31
AddrErr
TailErr
CurPErr
Error SOE SOP EngBusy
DS643_16_080307
Figure 35: Channel Status Register
Table 78: Channel Status Register
Bit(s)
Name
Core Reset
Access Value
0:9
Reserved
10
TailPErr
Read
0
11
CmpErr
Read
0
12
AddrErr
Read
0
13
NxtPErr
Read
0
14
CurPErr
Read
0
15
BsyWr
Read
0
Description
Reserved - Read as zero.
Tail Pointer Error: This bit indicates that Tail Pointer is NOT a valid address. Valid
addresses are between C_PI<Port_Num>_BASEADDR and
C_PI<Port_Num>_HIGHADDR.
Complete Error: This bit indicates a descriptor was fetched with the Cmplt = 1 in the
STS_CNTRL_APP0 field of the descriptor.
This error check is enabled by setting C_COMPLETED_ERR_RX and/or
C_COMPLETED_ERR_TX to 1 for the respective channel.
Address Error: This bit indicates the Current Buffer Address is NOT a valid address. Valid
addresses are between C_PI<Port_Num>_BASEADDR and
C_PI<Port_Num>_HIGHADDR.
Next Descriptor Pointer Error: This bit indicates the Next Descriptor Pointer is NOT a
valid address. Valid addresses are between C_PI<Port_Num>_BASEADDR and
C_PI<Port_Num>_HIGHADDR.
Current Descriptor Pointer Error: This bit indicates the Current Descriptor Pointer is NOT
a valid address.Valid addresses are between C_PI<Port_Num>_BASEADDR and
C_PI<Port_Num>_HIGHADDR.
Busy Write Error: This bit indicates the Current Descriptor Pointer register was written to
while the DMA Engine was busy.
DS643 February 22, 2013
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Product Specification