DS643 Datasheet, PDF (170/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
VFBC Synthesis Considerations
Table 91 shows the maximum frequency for the VFBC interface clocks, VFBC<Port_Num>_Cmd_Clk,
VFBC<Port_Num>_Wd_Clk, and VFBC<Port_Num>_Rd_Clk.
Table 91: Maximum VFBC Clock Frequencies by FPGA Family
FPGA Family
Clock Fmax
Notes
Spartan-3A DSP
133 MHz
With FIFO depths of 1024 32-bit words or fewer.
Virtex-4
Virtex-5
167 MHz
200 MHz
The VFBC interface clocks can have a higher or lower frequency than the MPMC_Clk0. Each VFBC interface is
asynchronous from the MPMC_Clk0 to support typical video clocks such as 27 MHz or 74.25 MHz. Higher
frequencies than those listed in Table 91 might be achievable but results depend on device, utilization, and VFBC
configuration.
VFBC Timing Constraints
The MPMC provides a Tcl script that generates the timing constraints within a UCF automatically for the VFBC
PIM. For the timing constraints to be set correctly, the clock frequency of MPMC_Clk0 must be specified in the MHS
file. The MHS file must have the CLK_FREQ value set for all input clock ports. The following code snippet is an
example of an MHS file PORT declaration showing the direction as Input (I) and the CLK_FREQ set:
PORT display_clk_pin = display_clk, DIR = I, SIGIS = CLK, CLK_FREQ = 27000000, BUFFER_TYPE =
IBUFG
If the clock frequency is not set, the automatically generated VFBC timing constraints assumes the frequencies listed
in Table 91 for the given device family.
Native Port Interface PIM
This NPI section covers the following topics:
• NPI PIM Features
• Connecting a Custom PIM to an NPI PIM
• NPI Design Restrictions and Recommendations
• NPI Clock Requirements
• Configuring the NPI PIM
• NPI Timing Diagrams
NPI PIM Features
The Native Port Interface (NPI) PIM:
• Allows you to extend the capabilities of MPMC to meet your own design needs.
• Offers a simple interface to memory that can be adapted to nearly any protocol.
• Provides address, data, and control signals to enable read and write requests for memory.
• Allows simultaneous push and pull of data from the port FIFOs.
• Has a configurable data width of 32 or 64 bits.
• When using 32-bit NPI, MPMC supports the following transfer sizes: byte, half-word, word, 4-word cacheline,
8-word cacheline, 16-word bursts, 32-word bursts, and 64-word bursts when using block RAM FIFOs. See
Restrictions on 64-Word Burst Transfers, page 173 for more information.
DS643 February 22, 2013
www.xilinx.com
170
Product Specification