DS643 Datasheet, PDF (62/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Alternatively, the mmcm_module can be replaced by a clock_generator core, as shown in the following code
example:
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 4.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 200000000
PARAMETER C_PSDONE_GROUP = MMCM0
PARAMETER C_CLKOUT0_FREQ = 400000000
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = MMCM0
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT1_FREQ = 200000000
PARAMETER C_CLKOUT1_PHASE = 0
PARAMETER C_CLKOUT1_GROUP = MMCM0
PARAMETER C_CLKOUT1_BUF = TRUE
PARAMETER C_CLKOUT2_FREQ = 400000000
PARAMETER C_CLKOUT2_PHASE = 0
PARAMETER C_CLKOUT2_GROUP = MMCM0
PARAMETER C_CLKOUT2_BUF = FALSE
PARAMETER C_CLKOUT2_VARIABLE_PHASE = TRUE
PARAMETER C_CLKOUT3_FREQ = 100000000
PARAMETER C_CLKOUT3_PHASE = 0
PARAMETER C_CLKOUT3_GROUP = MMCM0
PARAMETER C_CLKOUT3_BUF = TRUE
PORT CLKIN = sys_clk
PORT CLKOUT0 = MPMC_Clk_Mem
PORT CLKOUT1 = MPMC_Clk0
PORT CLKOUT2 = MPMC_Clk_Rd_Base
PORT CLKOUT3 = clk_100_0000MHzPLL0
PORT LOCKED = mmcm_0_lock
PORT PSCLK = MPMC_Clk0
PORT PSDONE = MPMC_DCM_PSDONE
PORT PSEN = MPMC_DCM_PSEN
PORT PSINCDEC = MPMC_DCM_PSINCDEC
PORT RST = sys_rst
END
Virtex-6 FPGA PIM Clocking
All PIMs have a base clock that is taken from the port MPMC_Clk0. MPMC_Clk0 must be shared across all PIMs. In
addition, some PIM types support an optional 1:1 or 1:2 clock ratio from their base PIM clock.
For example, it is possible to have an MPMC clocked as follows:
• MPMC_Clk_Mem = 400 MHz (400 MHz DDR2 or DDR3)
• MPMC_Clk0 = 200 MHz (synchronous to MPMC_Clk_Mem)
• Port 0 PLB PIM can connect to a PLB bus that must be 100 MHz (synchronous to MPMC_Clk0)
• Port 1 XCL PIM can connect to an XCL interface that must be 100 MHz (synchronous to MPMC_Clk0)
• Port 2 NPI PIM must run at 200 MHz using the same clock as MPMC_Clk0
DS643 February 22, 2013
www.xilinx.com
62
Product Specification