DS643 Datasheet, PDF (156/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Supported PLB Master and Bus Widths
Table 81 shows the supported PLB master and bus widths. A 32-bit NATIVE_DWIDTH PIM can only be used with a
PLB bus where all masters and slaves on the bus are 32 bits. The 32-bit NATIVE_DWIDTH PIM is intended for Spartan-3
FPGA based systems.
Table 81: Supported PLB Master and Bus Widths
C_SPLB<Port_Num>_NATIVE_DWIDTH=64
C_SPLB<Port_Num>_NATIVE_DWIDTH=32
C_SPLB<Port_Num>_DWIDTH
C_SPLB<Port_Num>_S
MALLEST_MASTER
Supported
C_SPLB<Port_Num>
_DWIDTH
C_SPLB<Port_Num>
_SMALLEST
_MASTER
Supported
128
128
Y
128
128
N
128
64
Y
128
64
N
128
32
Y
128
32
N
64
64
Y
64
64
N
64
32
Y
64
32
N
32
32
N
32
32
Y
To reduce the number of cycles between read transactions, the PLB v4.6 PIM can accept PLB read transactions when
SPLB<Port_Num>_PLB_SAValid is asserted. This allows a subsequent MPMC request to be asserted after the
current request has been acknowledged.
Configuring PLB v4.6 for Point-To-Point or Shared Bus
The PLB v4.6 PIM can be configured as either a Point-To-Point (P2P) configuration in which there is only one PLB
master communication with the PLB v4.6 PIM or a Shared Bus configuration:
• In P2P configuration, the PLB v4.6 PIM responds to all addresses regardless of the
C_PIM<Port_Num>_HIGHADDR and C_PIM<Port_Num>_BASEADDR parameter values. The PLB address is
decoded when the PLB v4.6 PIM is operating in a shared bus configuration only.
• In the Shared Bus configuration, the PLB v4.6 PIM can transfer data from up to 16 masters to the MPMC. An
extra cycle of latency is incurred when the PLB v4.6 PIM operates on a shared bus because PLB signals to the
PLB v4.6 PIM are registered to improve timing.
During memory initialization and calibration, the PIM asserts SPLB<Port_Num>_Sl_Wait or
SPLB<Port_Num>_Sl_Rearbitrate to hold off any PLB transactions until the memory is ready to process
transactions.
Configuring PLB v4.6 PIM SUBTYPES
You can configure the PLB v4.6 PIM with various SUBTYPEs to optimize it for a set of supported transactions. In
most cases the tools choose the appropriate PLB v4.6 PIM SUBTYPE automatically, based on the connectivity of the
system. The PLB v4.6 PIM SUBTYPEs are:
• 64-Bit Burst PIM
• Single word Read and Write transactions
• 4-word and 8-word, cacheline Read and Write transactions
• Fixed length burst transactions
• 32-Bit Burst PIM
• Single word Read and Write transactions
• 4-word and 8-word, cacheline Read and Write transactions
• Fixed length burst transactions
DS643 February 22, 2013
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Product Specification