DS643 Datasheet, PDF (100/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
*mpmc_phy_if_0/data_path/data_read/fifo_0_rd_addr_out<*><*>
*mpmc_phy_if_0/data_path/data_read/fifo_1_rd_addr_out<*><*>
c. PHY calibration tap values. These calibration values determine what delay is being applied to the DQS
signals to align the edges of the DQS strobe signal to the data.
*mpmc_phy_if_0/infrastructure/cal_top/cal_ctl/tapForDqs_rl<*>
Note: Regarding ChipScope tool usage: Attaching ChipScope tool probes onto signals that are used by the template
router could disrupt critical timing/routing nets. The ChipScope analyzer probes should be attached only to signals
operating in the MPMC_Clk0 and MPMC_Clk90 clock domain. The use of the ChipScope tool on a Spartan-3 device
could cause a conflict with the BSCAN element used for XMD access. This might require the use of XMD stub-based
debug or might require that a test program be initialized into LMB block RAM to generate the memory transactions.
6. Isolate which byte lanes are causing hangs or data errors and investigate those byte lanes further in greater
detail.
7. Implement the MPMC design using the Static PHY, get the static PHY to work, then compare results between
static PHY and MIG PHY. For example, Write with one PHY and Read with the other PHY to help isolate the
issue to Reads or Writes.
8. Run the standalone MIG hardware test bench design. This design consists of MIG PHY, controller, and
hardware test bench that loops write/read data to memory. The MIG hardware test bench design includes
preconfigured ChipScope tool probes and an error status LED output. If the standalone MIG test bench is not
working, resolve it first. The standalone MIG test bench is a smaller and simpler design that might be easier to
debug.
9. Verify that clock, control, data, power, and ground signals and board traces have the proper signal integrity and
implementation on the board.
Note: If you are not familiar with creating hardware and software designs as outlined in these steps, or you are unfamiliar with
the debug tool flows, practice building these designs using BSB and a supported Spartan-3 FPGA evaluation board such as the
Spartan-3A FPGA Starter Kit or the Spartan-3A DSP FPGA 1800 Starter Kit.
Board Considerations
The following sections describe the board considerations for Xilinx or third-party boards:
• Important Notes on MIG Board Compatibility
• Tips and Hints for Board Bring Up
Important Notes on MIG Board Compatibility
Many existing evaluation boards were developed before the MIG tool was finalized, so it is often the case that Xilinx
or third-party evaluation boards do not have exactly the same pinout that would be generated by supported MIG
versions. However, these boards usually come with a predefined MPMC UCF that is suitable for that board to
function correctly.
Some Xilinx boards, including the Spartan-3E FPGA Starter Kit (XC3S500E), Spartan-3E FPGA 1600E MicroBlaze
Development Kit, and the Spartan-3A/3AN FPGA Starter Kit boards, have a pinout that significantly deviates from
normal MIG pinout assignment rules.
For these boards, a parameter to the MPMC called C_SPECIAL_BOARD is used to modify the internal PHY logic to
compensate for the memory pinout on these boards. A predefined MPMC UCF is needed for these boards. Systems
created using the BSB have the necessary C_SPECIAL_BOARD and UCF settings. Having more severe MIG pinout
violations means the Spartan-3E FPGA Starter Kit (XC3S500E) and Spartan-3E FPGA 1600 MicroBlaze
Development Kit should not have their memory clocks run above 100 MHz. Other boards, including the Virtex-5
FXT FPGA ML507 Evaluation Platform, might also have a sub-optimal pinout that limits the maximum operating
frequency of the memory interface.
DS643 February 22, 2013
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Product Specification