DS643 Datasheet, PDF (37/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 32: Virtex-4 FPGA MIG PHY Debug Registers (Cont’d)
Register Name
Base Address/
Offset from
C_MPMC_CTRL
BASEADDR (in hex)
Bits
0:31
Field Name
Access
Type
0:7 DQ_IN_BYTE_ALIGN<n> R/W
V4_CALIB_DQS_
GROUP0
11:15 RDEN_DLY<n>
R/W
.
0x2140
.
...
.
0x2160 16:29 unused
V4_CALIB_DQS_
GROUP8
30 DELAY_RD_FALL<n>
R/W
31 RD_SEL<n>
R/W
V4_CALIB_DQS_
TAP_GROUP0
.
.
.
V4_CALIB_DQS_
TAP_GROUP8
0:6 unused
7 DQS_TAP_CNT_INC<n> Wr Only
0x2180
.
.
.
0x21a0
8:14
15
16:25
unused
DQS_TAP_CNT_DEC<n>
unused
Wr Only
26:31 DQS_TAP_CNT<n>
R
0x2200 ^{0:22 unused}
V4_CALIB_DQ_
TAP_COUNT<n>
.
.
.
23 DQ_DELAY_EN<n>
W
0x231C _{24:31 unused}
Default
Value
0
0
0
N/A
N/A
0
0
Description
Calibration bit alignment of 8 bits within
the byte.
0 = bits aligned or align bits
1 = no bit alignment
Related MIG PHY signal:
DELAY_ENABLE
Number of cycles after read command
until read data is valid for DQS group<n>.
Related MIG PHY signal:
CLK_COUNT
Indicates relative alignment of bytes for
DQS group<n>.
Related MIG PHY signal:
DELAY_RD_FALL
Final read capture MUX set for positive or
negative edge capture for DQS group<n>.
Related MIG PHY signal:
FIRST_RISING
DQS<n> IDELAY tap count increment,
1 tap increment per write.
DQS<n>IDELAY tap count decrement,
1 tap decrement per write.
DQS<n>IDELAY tap count.
0 = Pass
1 = Fail
DQ<n> alignment of bits within a byte
lane
DS643 February 22, 2013
www.xilinx.com
37
Product Specification