DS643 Datasheet, PDF (66/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
ECC Read Data Handling
On Reads, data passes through the ECC Error Detection and Correction block. The data is checked for errors. If
there are no errors, data passes through as normal and goes into the Read FIFO as a normal read. If a single error is
detected, the error is corrected automatically (SEC) and sent to the Read FIFO to complete as a normal read. If two
errors are detected (DED), the data is not corrected but passed through unchanged and reported to the Control and
Status registers.
ECC Need for Read Modify Write
During writes to memory, a new set of ECC check bits must be written to memory along with write data. The ECC
encoding process is handled by the ECC Check Bit Encode block. Read-Modify-Writes (RMW) operations are
needed for write transactions where the byte enables that span the width of the ECC word on the SDR bus are not
all On or Off. Because many ECC DIMMs do not have Data Mask (DM) pins, the RMW is required.
When byte enables do not exist or are not all On or all Off, the correct value of the ECC check bits are not known
because not all the data across the ECC word is present.
The RMW operation first fetches the data value of the masked off byte lanes so the correct ECC check bits for the
whole ECC word can be computed and written. RMW is accomplished by taking read data (after ECC decode and
correction) and storing the data in a FIFO that is the same width as the SDR data bus. Later, as write data comes out
of the Write FIFO, the masked off byte enables activate an MUX that routes read data to fill in the corresponding
“holes” in the write data. The result is a complete set of data with which to compute the new ECC check bits. All
resultant data is written to memory. Consequently, writes with any byte enables turned Off result in writes with all
byte enables turned On. This has the side effect that masked-off write data is read, scrubbed, and written back.
The Control state machine is modified during a RMW operation to perform a full Read and then a full Write.
Because the data is on the same memory page, an optimization is to skip the precharge and activate commands
between a read and a write. To optimize the space in the control path block RAM state machines, RMW operations
reuse the corresponding Read and Write state machines for the given transfer size. Special block RAM state
machine bits are used to implement the chained RMW operation and to skip precharge and activate commands.
The RMW process does add latency to the design because a full Read must precede a Write. This can double the
transaction time for Writes. Writes with all byte enables On or all Off are faster than Writes with mixed byte enables
due to need for RMW. A flag bit is introduced into the NPI interface to allow the transactions to be qualified as
needing or not needing RMW.
The PIM<Port_Num>_RdModWr flag bit informs the MPMC if transactions require RMW (= 1) or do not require
RMW (= 0). The PIM<Port_Num>_RdModWr signal must be asserted with PIM<Port_Num>_AddrReq. The
PIM<Port_Num>_RdModWr signal should be asserted with respect to the memory burst length of 4 and the ECC
word size of the memory interface being used. Any NPI transfer sizes which are less than a four beat memory burst
must assert PIM<Port_Num>_RdModWr.
For NPI interfaces that do not support the RMW, or are not able to set it dynamically, the value should default to 1
to ensure correct Write operations under all conditions. Dynamic RMW allows for write performance to be
optimized when RMW is known to not be needed.
If all the byte enables are Off but a RMW operation is performed, data is still read, scrubbed, and written back.
This would permit a custom NPI device to perform burst writes with byte enables all Off (and RdModWr = 1) to scrub
memory. The MPMC does not require the memory to support DM pins with ECC. DM pins can be connected, if
needed, or left unconnected.
DS643 February 22, 2013
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Product Specification