DS643 Datasheet, PDF (158/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 82: Supported Transactions (Cont’d)
SPLB_PLB_SIZE
[0:3]
Description
SPLB_PLB_TYPE[0:2]
Indeterminate Burst
000b
001b-111b
Memory Transfer
N/A
Burst request of 2-16 databeats
Burst request of > 16 databeats
Read/Write
Read
Write
Read
Read
Write
Read
Write
Read
Write
C_PIM<Port_Num>_SUBTYPE
PLB DPLB IPLB Single
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
Y
N
N
N
Y
N
N
N
N
N
N
N
N
N
N
N
PowerPC 440 Processor Memory Controller PIM
The PowerPC 440 processor Memory Controller (PPC440MC) PIM connects MPMC directly to the memory
interface port of the PowerPC 440 block in Virtex-5 FXT devices.
Note: The ppc440mc_ddr2 IP core should be used instead of MPMC whenever possible. The ppc440mc_ddr2 IP core is
optimized as a single port DDR2 memory for the PowerPC 440 processor memory interface. The ppc440mc_ddr2 IP core
offers lower latency and higher Fmax than the MPMC. The MPMC should only be used when SDRAM/DDR memory support or
multiple memory ports are needed.
This topic contains the following subsections:
• PPC440MC Features
• Supported PPC440MC Interface Configuration
• PPC440MC Overview
• PPC440MC Design Implementation
• PPC440MC Parameter and Port Dependencies
• PPC440MC Burstwidth and Burstlength by Memory Type/Width Dependencies
PPC440MC Features
• Supports the Virtex-5 FPGA, V5FXT, memory interface.
• Supports 32-bit and 64-bit NPI interfaces using 32-bit and 64-bit PPC440MC data widths.
• Runs with 1:1 clocking with NPI and MIB.
• Provides parameterized burst sizes of 2, 4, and 8.
• Supports read data latency of 0, 1, and 2 clocks.
• Can operate at a 1:1, 1:2, 1:3, or 1:4 clock ratio with respect to the PowerPC processor crossbar interconnect
clock (CPMINTERCONNECTCLK)
Supported PPC440MC Interface Configuration
The PPC440MC PIM requires the following configuration settings shown in Table 83 in the MI_CONTROL register of
the PowerPC 440 processor block. It is recommended to set the initial value using the C_PPC440MC_CONTROL MHS
parameter of the PPC440 instance.
DS643 February 22, 2013
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158
Product Specification