DS643 Datasheet, PDF (172/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
If one of these cases exists, the following restrictions must be adhered to:
• The PIM<Port_Num>_WrFIFO_Push must occur a minimum of one cycle after the PIM<Port_Num>_AddrAck
when requesting either a byte, half-word, word or double-word write transfer.
• Any PIM<Port_Num>_WrFIFO_Push corresponding to previous requests must be asserted before requesting a
new byte, half-word, word or double-word write transfer.
Restrictions between PIM<Port_Num>_AddrReq and PIM<Port_Num>_WrFIFO_Push
Due to the definition of PIM<Port_Num>_AddrReq, write data must be pushed into the write FIFOs before it is
required by the memory. For safest operation, assert the address request after all data has been pushed into the
write FIFOs, as shown in 64-bit NPI Timing Diagrams, page 174. See the Restrictions on Byte, Half-Word, Word, and
Doubleword Write Transfers, page 171 for exceptions.
Restrictions on Pipelining of Address Requests
A FIFO that is controlling the PIM<Port_Num>_RdFIFO_RdWdAddr signal stores up to four read address requests
only, regardless of transfer size; consequently, an NPI master is not allowed to queue more than four read requests
without popping the corresponding data out of the Read FIFO.
Restrictions on Address Alignment
NPI transactions must have the PIM<Port_Num>_Addr address aligned to the size of the transactions, as specified by
PIM<Port_Num>_Size. For example, a 32-word burst must have PIM<Port_Num>_Addr[6:0] set to 0.
Burst Writes to unaligned addresses can be performed by Writing pad data to PIM<Port_Num>_WrFIFO_Data and
preventing the corresponding data from being committed by deasserting PIM<Port_Num>_WrFIFO_BE. See Address
Path, page 55 for address alignment requirements.
Restrictions on SRL FIFOs
The user logic must prevent write FIFO overflows for NPI writes, facilitated by the use of the
PIM<Port_Num>_WrFIFO_AlmostFull signal. The MPMC does not prevent Read FIFO overflows when using the
SRL FIFOs. The SRL FIFO can hold up to 64 words (64-bit NPI) or 32 words (32-bit NPI). Depending on the burst
sizes being used, ensure that the total size of outstanding Read requests does not exceed the capacity of the SRL
FIFO. For example, if 32-word bursts and 64-bit NPI are used, do not request more that two transactions with
PIM<Port_Num>_AddrReq before reading out all 32 words of data from the first transaction.
Restrictions on Block RAM FIFOs
The implementation of block RAM FIFOs does not contain a valid PIM<Port_Num>_WrFIFO_AlmostFull signal,
nor automatic throttling of PIM<Port_Num>_AddrAck during Reads. These optimizations were performed to
improve the maximum MPMC clock frequency and result in restrictions for both NPI Reads and Writes as follows:
• For Reads, MPMC with block RAM FIFOs does not check how much data is in the Read FIFO before asserting
the address acknowledge; consequently, an NPI master is not allowed to queue Read requests that total more
than 1024 bytes of data without popping the corresponding data out of the FIFOs. The Read FIFOs hold up to
1024 bytes of data, corresponding to four 64-word transfers. A further 64-word read request without popping
earlier requests will overflow the read FIFO past 1024 bytes of data.
• For Writes, the NPI master is not allowed to queue up more than 1024 bytes of data in the Write FIFOs and the
PIM<Port_Num>_WrFIFO_AlmostFull signal cannot be used.
Consequently, there are options for ensuring the FIFOs do not overflow:
- The first option is to push 1024 or less bytes of data into the Write FIFO, perform all address requests
associated with this data, and then wait for the PIM<Port_Num>_WrFIFO_Empty to be asserted before
pushing more data.
DS643 February 22, 2013
www.xilinx.com
172
Product Specification