DS643 Datasheet, PDF (186/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
8-Word, Cacheline Write
Figure 55 shows the following:
• A 32-bit NPI.
• An 8-word, cacheline Write transfer.
• The address is acknowledged in the same cycle as it is requested.
• The address is on an 8-word boundary.
• The RdModWr does not need to be asserted because WrFIFO_BE is 0xF during WrFIFO_Push, and because the
8-word transfer is larger than the maximum value of 4*C_MEM_DATA_WIDTH.
• The Write Transfer Safe Mode is used (AddrReq is asserted on the same cycle as the last WrFIFO_push).
X-Ref Target - Figure 55
MPMC_CLK0
AddrReq
AddrAck
Addr[31:0]
0x20
RNW
Size[3:0]
0x2
RdModWr
InitDone
WrFIFO_Empty
WrFIFO_AlmostFull
WrFIFO_Push
WrFIFO_Flush
WrFIFO_Data[31:0]
WrFIFO_BE[3:0]
D0
D1
D2
D3
D4
D5
D6
D7
0xF
Figure 55: 32-Bit NPI 8-Word Cacheline Write
DS643_48_072407
DS643 February 22, 2013
www.xilinx.com
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Product Specification