DS643 Datasheet, PDF (11/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 3: Memory and Memory Part Parameters (Cont’d)
Parameter Name
C_ECC_DEC_THRESHOLD⁽⁶⁾
C_ECC_DEFAULT_ON⁽⁶⁾
C_ECC_DM_WIDTH^(5),(6)
C_ECC_DQS_WIDTH^(5),(6)
C_INCLUDE_ECC_SUPPORT
C_INCLUDE_ECC_TEST⁽⁶⁾
C_ECC_PEC_THRESHOLD⁽⁶⁾
C_ECC_SEC_THRESHOLD⁽⁶⁾
Default Value
1
1
0
0
0
0
1
1
Allowable Values
0-4095
0,1
0,1
0,1
0,1
0,1
0-4095
0-4095
Description
Double-bit data error interrupt threshold
counter value.
Enables ECC enable register at RST.
ECC DM width.
ECC DQS width.
Enables ECC logic. ECC control registers
are accessible from MPMC_CTRL interface
when enabled. Not supported on Virtex-6 or
Spartan-6 families.
Enable or disable ECC test functionality and
registers:
1 = Enable ECC test functionality/registers.
0 = No ECC test functionality (saves area).
Specifies the parity-bit data error interrupt
threshold counter value.
Single-bit data error interrupt threshold
counter value.
Notes:
1. These values are auto-updated from the IP Configuration database if C_MEM_PARTNO is set to a part number from the database. If set to
CUSTOM, the values must be filled in according to the memory parameters provided by the manufacturer. Used for Spartan-3, Virtex-4, and
Virtex-5 families. The database is a Comma Separated Value (CSV) file located at <MPMC pcore
location>/data/mpmc_memory_database.csv. For Spartan-6 and Virtex-6 FPGAs, the database is obtained from MIG and contains
only approved memories for each architecture. Spartan-6 FPGAs do not support CUSTOM memory parts.
2. DDR parameter.
3. DDR2 parameter.
4. CAS latencies/Fmax pairs should be arranged from Lowest CAS Latency and Slowest Frequency to Highest CAS Latency and Fastest
frequency for pairs A-D.
5. Non-user, auto-calculated value.
6. Valid if C_INCLUDE_ECC_SUPPORT is enabled
7. The use of Multi-Rank designs is strongly discouraged
See Important Notes on MIG Board Compatibility, page 100 for more information.
8. SDMA supports all configurations on Spartan-6 and Virtex-6 FPGAs. All other architectures support the following configurations only:
• 32- and 64-bit for DDR.
• 64-bit for SDRAM.
9. Spartan-6 FPGAs only.
10. Virtex-6 FPGAs only.
11. DDR3 only.
12. Not used for Spartan-6 FPGAs.
13. ODT is required for Virtex-6 FPGA DDR2/DDR3 memories. A value of 0 (Disabled) is not a valid option for this parameter when targeting
the Virtex-6 family.
14. Reserved. Low-level parameter for underlying Spartan-6 FPGA MCB. This setting should not be changed.
15. Reserved. Low-level parameter for underlying Virtex-6 FPGA MIG PHY. This setting should not be changed.
16. Parameter is set automatically when C_USE_MIG_FLOW = 1.
DS643 February 22, 2013
www.xilinx.com
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Product Specification